SPRUJ66B February   2023  – September 2025

 

  1.   1
  2.   Description
  3.   Get Started
  4.   Features
  5.   Applications
  6.   6
  7. 1Evaluation Module Overview
    1. 1.1 Introduction
    2. 1.2 Kit Contents
    3. 1.3 Specification
      1. 1.3.1 Key Features
        1. 1.3.1.1 Processor
        2. 1.3.1.2 Memory
        3. 1.3.1.3 JTAG Emulator
        4. 1.3.1.4 Supported Interfaces and Peripherals
        5. 1.3.1.5 Expansion Connectors Headers to Support Application Specific Add On Boards
    4. 1.4 Device Information
  8. 2Hardware
    1. 2.1 EVM Revisions and Assembly Variants
    2. 2.2 System Description
      1. 2.2.1 Board Image With Markings
      2. 2.2.2 Functional Block Diagram
      3. 2.2.3 AM62A Low Power SK EVM Interface Mapping
      4. 2.2.4 Power ON/OFF Procedures
        1. 2.2.4.1 Power-On Procedure
        2. 2.2.4.2 Power-Off Procedure
        3. 2.2.4.3 Power Test Points
      5. 2.2.5 Peripheral and Major Component Description
        1. 2.2.5.1  Clocking
          1. 2.2.5.1.1 Peripheral Ref Clock
        2. 2.2.5.2  Reset
        3. 2.2.5.3  CSI Interface
        4. 2.2.5.4  Audio Codec Interface
        5. 2.2.5.5  HDMI Display Interface
        6. 2.2.5.6  JTAG Interface
        7. 2.2.5.7  Test Automation Header
        8. 2.2.5.8  UART Interface
        9. 2.2.5.9  USB Interface
          1. 2.2.5.9.1 USB 2 0 Type A Interface
          2. 2.2.5.9.2 USB 2 0 Type C Interface
        10. 2.2.5.10 Memory Interfaces
          1. 2.2.5.10.1 LPDDR4 Interface
          2. 2.2.5.10.2 Octal Serial Peripheral Interface (OSPI)
          3. 2.2.5.10.3 MMC Interfaces
            1. 2.2.5.10.3.1 MMC0 - eMMC Interface
            2. 2.2.5.10.3.2 MMC1 - Micro SD Interface
            3. 2.2.5.10.3.3 MMC2 - M.2 Key E Interface
          4. 2.2.5.10.4 Board ID EEPROM
        11. 2.2.5.11 Ethernet Interface
          1. 2.2.5.11.1 CPSW Ethernet PHY Default Configuration
        12. 2.2.5.12 GPIO Port Expander
        13. 2.2.5.13 GPIO Mapping
        14. 2.2.5.14 Power
          1. 2.2.5.14.1 Power Requirements
          2. 2.2.5.14.2 Power Input
          3. 2.2.5.14.3 Power Supply
          4. 2.2.5.14.4 AM62A SoC Power
          5. 2.2.5.14.5 Current Monitoring
        15. 2.2.5.15 AM62A Low Power SK EVM User Setup and Configuration
          1. 2.2.5.15.1 Boot Modes
          2. 2.2.5.15.2 User Test LEDs
        16. 2.2.5.16 Expansion Headers
          1. 2.2.5.16.1 User Expansion Connector
          2. 2.2.5.16.2 MCU Connector
        17. 2.2.5.17 I2C Address Mapping
  9. 3Hardware Design Files
    1. 3.1 Schematics, PCB Layout and BOM
  10. 4Additional Information
    1. 4.1 Known Hardware or Software Issues
    2. 4.2 EMC, EMI, and ESD Compliance
    3. 4.3 Trademarks
    4.     72
  11. 5Revision History

1.1 Introduction

This evaluation module user's guide is an excellent resource for those looking to develop applications with TI's AM62A Low-Power SK EVM. This low-cost Starter Kit is built around TI's AM62A AI Vision processor which includes an image signal processor (ISP) supporting 5MP@60FPS, 2 tera-operations-per-second (TOPS) AI Accelerator, Quad-Core 64-bit Arm-Cortex A53 microprocessor, Single-Core Arm Cortex-R5F, and H.264/H.265 video encode/decode. The SK-AM62A-LP is an ideal choice for those looking to develop smart camera, dashcam, machine vision camera, and automotive front camera applications.

The starter kit also includes both a MIPI CSI-2 camera connector for a single camera and additional expansion connector for up to four cameras, making it suitable for a variety of embedded vision and AI applications on the edge. For a variety of applications, TI's ISP can handle different lighting conditions in video streams by using HDR encoding and RBG-IR camera support. With the help of edge AI, Deep Learning on video streams like image classification and object detection have greatly improved performance on AM62A's AI accelerator. Therefore, giving significant improvement in frame rate, latency, and performance to allow offloading intensive processes from general purpose cores.

Furthermore, the starter kit supports Linux development with feature rich EdgeAI SDK. On-chip emulation logic allows for emulation and debugging using standard development tools such as Code Composer Studio™ from TI.

Note: This evaluation board is a pre-production release and has a few known issues that should not be copied into a production system.

SK-AM62A-LP also includes both a mobile industry processor interface (MIPI®) CSI-2 camera connector for a single camera and an additional expansion connector for up to four cameras, making it suitable for a variety of embedded vision and AI applications on the edge. For a variety of applications, our ISP can handle different lighting conditions in video streams by using high dynamic range (HDR) encoding and RGB-IR camera support. With edge AI, deep learning on video streams like image classification and object detection have greatly improved performance on the AM62A AI accelerator, therefore giving significant improvement in frame rate, latency and performance to allow offloading intensive processes from general-purpose cores.

Furthermore, the SK-AM62A-LP supports Linux® development with a feature-rich edge AI software development kit (SDK). On-chip emulation logic allows for emulation and debugging using standard development tools such as the Code Composer Studio integrated development environment (IDE) (CCSTUDIO) as well as an intuitive out-of-box user's guide to quickly start design evaluation.

During custom board design, customers tend to reuse the SK design files and make edits to the design file. Alternatively customers reuse some of the common implementations including the SOC, memory and communication interfaces. Since the SK is expected to have additional functionalities, customers optimize the SK implementation to suit their board design requirements. While optimizing the SK schematics, errors get introduced into the custom design that can cause functional, performance or reliability issues. When optimizing customers have queries regarding the SK implementation resulting in design errors. Many of the optimization and design errors are common across designs. Based on the learnings and data sheet pin connectivity recommendations, comprehensive Design Notes (D-Note:), Review Notes (R-Note:) and Cad Notes (Cad Note:) have been added near each section of the SK schematic that customers can review and follow to minimize errors. Additional files as part of the design downloads have been included to support customer evaluation.