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|*||Data sheet||CDCM9102 Low-Noise Two-Channel 100-MHz Clock Generator datasheet (Rev. A)||PDF | HTML||25 Apr 2016|
|Technical article||How to select an optimal clocking solution for your FPGA-based design||09 Dec 2015|
|Technical article||Clocking sampled systems to minimize jitter||31 Jul 2014|
|Technical article||Timing is Everything: How to optimize clock distribution in PCIe applications||28 Mar 2014|
|EVM User's guide||CDCM9102EVM Evaluation Module||27 Feb 2012|
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|VQFN (RHB)||32||View options|
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