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CDCM9102

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Low noise two channel 100-MHz PCIe clock generator

Data sheet
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Low noise two channel 100-MHz PCIe clock generator

CDCM9102

ACTIVE
Data sheet Order now

Product details

Parameters

Function Clock generator Number of outputs 2 Output frequency (Max) (MHz) 1296 Core supply voltage (V) 3.3 Output supply voltage (V) 3.3 Input type LVPECL Output type LVDS Operating temperature range (C) -40 to 85 Features 3.3-V VCC/VDD, Pin programmable Rating Catalog open-in-new Find other Clock generators

Package | Pins | Size

VQFN (RHB) 32 25 mm² 5 x 5 open-in-new Find other Clock generators

Features

  • Integrated Low-Noise Clock Generator Including
    PLL, VCO, and Loop Filter
  • Two Low-Noise 100-MHz Clocks (LVPECL,
    LVDS, or pair of LVCMOS)
    • Support for HCSL Signaling Levels
      (AC-Coupled)
    • Typical Period Jitter: 21 ps pk-pk
    • Typical Random Jitter: 510 fs RMS
    • Output Type Set by Pins
  • Bonus Single-Ended 25-MHz Output
  • Integrated Crystal Oscillator Input Accepts
    25-MHz Crystal
  • Output Enable Pin Shuts Off Device and Outputs
  • 5-mm × 5-mm 32-Pin VQFN Package
  • ESD Protection Exceeds 2000 V HBM, 500 V
    CDM
  • Industrial Temperature Range (–40°C to 85°C)
  • 3.3-V Power Supply
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Description

The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 5
Type Title Date
* Datasheet CDCM9102 Low-Noise Two-Channel 100-MHz Clock Generator datasheet (Rev. A) Apr. 25, 2016
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Technical articles Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical articles Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
User guide CDCM9102EVM Evaluation Module Feb. 27, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
199
Description

CDCM9102EVM is the evaluation module for CDCM9102, a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express. The device is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for (...)

Features
  • Easy-to-use evaluation module to generate clock signals with low jitter and phase noise
  • Easy device setup
  • Control pins configurable through jumpers
  • Requires 3.3-V power supply
  • Single-ended or crystal input clock reference
  • Termination available for LVPECL, LVDS, and LVCMOS output clocks
View details
EVALUATION BOARD Download
1146.54
Description
J6Entry, RSP and TDA2E-17 CPU Board EVM is an evaluation platform designed to speed up development efforts and reduce time to market for Infotainment  reconfigurable Digital Cluster or Integrated Digital Cockpit and ADAS applications. The CPU board integrates key peripherals such as parallel (...)
Features
  • 2GB DDR3L
  • LP8733/LP8732 Power Solution
  • On-board eMMC, NAND, NOR
  • USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
View details
EVALUATION BOARD Download
2324.44
Description

The J6Entry/RSP EVM is an evaluation platform designed to speed up development efforts and reduce time to market for applications such as Infotainment, reconfigurable Digital Cluster or Integrated Digital Cockpit.

The main CPU board integrates these key peripherals such as Ethernet or HDMI, while the (...)

Features
  • 10.1" Display with capacitive Touch
  • JAMR3 Radio Tuner Application Board
  • 2GB DDR3L
  • LP8733/LP8732 Power Solution
  • On-board eMMC, NAND, NOR
  • USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
View details

Design tools & simulation

SIMULATION MODEL Download
SCAM055.ZIP (64 KB) - IBIS Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
View details

Reference designs

REFERENCE DESIGNS Download
Industrial Communications Gateway PROFINET IRT to PROFIBUS Master Reference Design
TIDEP-0075 — PROFINET is becoming the leading industrial Ethernet protocol in automation due to its high-speed, deterministic communications and enterprise connectivity. However, as the world’s most popular fieldbus, PROFIBUS’s importance and usage will continue for many years due to legacy (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
OPC UA Data Access Server for AM572x Reference Design
TIDEP0078 — OPC UA is an industrial machine-to-machine protocol designed to allow interoperability and communication between all machines connected under Industry 4.0. The TIDEP0078 TI Design demonstrates use of the MatrikonOPC™ OPC UA server development kit (SDK) to allow communications using an OPC UA (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
3D Machine Vision Reference Design Based on AM572x Processor with DLP® Structured Light
TIDEP0076 — The TIDEP0076 3D machine vision design describes an embedded 3D scanner based on the structured light principle. A digital camera along with a Sitara™ AM57xx processor System on Chip (SoC)  is used to capture reflected light patterns from a DLP4500-based projector. Subsquent processing of (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Monte-Carlo Simulation on AM57x Using OpenCL for DSP Acceleration Reference Design
TIDEP0046 — TI’s high performance ARM® Cortex®-A15 based AM57x processors also integrate C66x DSPs. These DSPs were designed to handle high signal and data processing tasks that are often required by industrial, automotive and financial applications. The AM57x OpenCL implementation makes it easy (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Power and Thermal Design Considerations Using TI's AM57x Processor Reference Design
TIDEP0047 — This TI Design (TIDEP0047) is a reference platform based on the AM57x processor and companion TPS659037 power management integrated circuit (PMIC).  This TI Design specifically highlights important power and thermal design considerations and techniques for systems designed with AM57x and (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RHB) 32 View options

Ordering & quality

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  • MTBF/FIT estimates
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  • Qualification summary
  • Ongoing reliability monitoring

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