Low noise two channel 100-MHz PCIe clock generator
Product details
Parameters
Package | Pins | Size
Features
- Integrated Low-Noise Clock Generator Including
PLL, VCO, and Loop Filter - Two Low-Noise 100-MHz Clocks (LVPECL,
LVDS, or pair of LVCMOS)- Support for HCSL Signaling Levels
(AC-Coupled) - Typical Period Jitter: 21 ps pk-pk
- Typical Random Jitter: 510 fs RMS
- Output Type Set by Pins
- Support for HCSL Signaling Levels
- Bonus Single-Ended 25-MHz Output
- Integrated Crystal Oscillator Input Accepts
25-MHz Crystal - Output Enable Pin Shuts Off Device and Outputs
- 5-mm × 5-mm 32-Pin VQFN Package
- ESD Protection Exceeds 2000 V HBM, 500 V
CDM - Industrial Temperature Range (–40°C to 85°C)
- 3.3-V Power Supply
Description
The CDCM9102 is a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express™. The device supports up to PCIE gen3 and is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for these ports include LVPECL, LVDS, or a pair of LVCMOS buffers. HCSL signaling is supported using an AC-coupled network. The user configures the output buffer type desired by strapping device pins. Additionally, a single-ended 25-MHz clock output port is provided. Uses for this port include general-purpose clocking, clocking Ethernet PHYs, or providing a reference clock for additional clock generators. All clocks generated are derived from a single external 25-MHz crystal.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | CDCM9102 Low-Noise Two-Channel 100-MHz Clock Generator datasheet (Rev. A) | Apr. 25, 2016 |
Technical articles | How to select an optimal clocking solution for your FPGA-based design | Dec. 09, 2015 | |
Technical articles | Clocking sampled systems to minimize jitter | Jul. 31, 2014 | |
Technical articles | Timing is Everything: How to optimize clock distribution in PCIe applications | Mar. 28, 2014 | |
User guide | CDCM9102EVM Evaluation Module | Feb. 27, 2012 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Hardware development
Description
CDCM9102EVM is the evaluation module for CDCM9102, a low-jitter clock generator designed to provide reference clocks for communications standards such as PCI Express. The device is easy to configure and use. The CDCM9102 provides two 100-MHz differential clock ports. The output types supported for (...)
Features
- Easy-to-use evaluation module to generate clock signals with low jitter and phase noise
- Easy device setup
- Control pins configurable through jumpers
- Requires 3.3-V power supply
- Single-ended or crystal input clock reference
- Termination available for LVPECL, LVDS, and LVCMOS output clocks
Description
Features
- 2GB DDR3L
- LP8733/LP8732 Power Solution
- On-board eMMC, NAND, NOR
- USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
Description
The J6Entry/RSP EVM is an evaluation platform designed to speed up development efforts and reduce time to market for applications such as Infotainment, reconfigurable Digital Cluster or Integrated Digital Cockpit.
The main CPU board integrates these key peripherals such as Ethernet or HDMI, while the (...)
Features
- 10.1" Display with capacitive Touch
- JAMR3 Radio Tuner Application Board
- 2GB DDR3L
- LP8733/LP8732 Power Solution
- On-board eMMC, NAND, NOR
- USB3, USB2, PCIe, Ethernet, COM8Q, CAN, MLB, MicroSD and HDMI connectors
Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
Reference designs
Design files
-
download AM572x Industrial Development Kit (IDK) Bill of Materials (BOM).zip (31KB) -
download AM572x Industrial Development Kit (IDK) Assembly Drawing Files.zip (606KB) -
download AM572x Industrial Development Kit (IDK) Design Files (CAD).zip (19060KB) -
download AM572x Industrial Development Kit (IDK) Gerber Files.zip (10113KB) -
download AM572x Industrial Development Kit (IDK) Design Files (CAD) (Rev. A).pdf (6325KB) -
download AM572x Industrial Development Kit (IDK) Gerber Files (Rev. A).zip (1495KB)
Design files
-
download AM572x Industrial Development Kit (IDK) Bill of Materials (BOM).zip (31KB) -
download AM572x Industrial Development Kit (IDK) Assembly Drawing Files.zip (606KB) -
download AM572x Industrial Development Kit (IDK) Design Files (CAD).zip (19060KB) -
download AM572x Industrial Development Kit (IDK) Gerber Files.zip (10113KB) -
download OPC UA Data Access Server for AM572x BOM.pdf (110KB) -
download OPC UA Data Access Server for AM572x Assembly Files.zip (607KB) -
download OPC UA Data Access Server for AM572x CAD Files.zip (7084KB) -
download OPC UA Data Access Server for AM572x Gerber.zip (10114KB) -
download AM572x Industrial Development Kit (IDK) Design Files (CAD) (Rev. A).pdf (6325KB) -
download AM572x Industrial Development Kit (IDK) Gerber Files (Rev. A).zip (1495KB)
Design files
Design files
Design files
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
VQFN (RHB) | 32 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Recommended products may have parameters, evaluation modules or reference designs related to this TI product.
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