CDCM9102

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Low Noise Two Channel 100MHz PCIe Clock Generator

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Type Title Date
* Datasheet CDCM9102 Low-Noise Two-Channel 100-MHz Clock Generator datasheet (Rev. A) Apr. 25, 2016
Selection guides Clock & Timing Solutions (Rev. C) Jan. 19, 2017
Technical articles How to select an optimal clocking solution for your FPGA-based design Dec. 09, 2015
Selection guides Analog for Xilinx (R) FPGAs Selection Guide - 2015 (Rev. B) Jan. 07, 2015
Technical articles Clocking sampled systems to minimize jitter Jul. 31, 2014
Technical articles Timing is Everything: How to optimize clock distribution in PCIe applications Mar. 28, 2014
User guides CDCM9102EVM Evaluation Module Feb. 27, 2012