Product details


Function Serializer Color depth (bpp) 24 Pixel clock min (MHz) 25 Pixel clock (Max) (MHz) 185 Input compatibility LVCMOS Output compatibility FPD-Link LVDS Features Drives QXGA and WQXGA Class Displays, Three Operating Modes (SISO, SIDO, DIDO), Dual pixel architecture, Sleep Mode, Optional Low Power Mode Signal conditioning VOD Select EMI reduction LVDS, SSC Compatibility Diagnostics Total throughput (Mbps) 5565 Rating Catalog Operating temperature range (C) -10 to 70 open-in-new Find other Display SerDes

Package | Pins | Size

VQFN-MR (NLA) 92 49 mm² 7 x 7 open-in-new Find other Display SerDes


  • 100 mW Typical Power Consumption at 185 MHz (SIDO Mode)
  • Drives QXGA and WQXGA Class Displays
  • Three Operating Modes:
    • Single Pixel In, Single Pixel Out (SISO): 105 MHz Maximum
    • Single Pixel In, Dual Pixel Out (SIDO): 185 MHz Maximum
    • Dual Pixel In, Dual Pixel Out (DIDO): 105MHz
  • Supports 24-Bit RGB, 48-Bit RGB
  • Optional low Power Mode Supports 18-Bit RGB, 36-Bit RGB
  • Supports 3D+C, 4D+C, 6D+C, 6D+2C, 8D+C, and 8D+2C LVDS Configurations
  • Compatible With FPD-Link Deserializers
  • Operates Off a Single 1.8-V Supply
  • Interfaces Directly With 1.8-V LVCMOS
  • Less Than 1 mW Power Consumption in Sleep Mode
  • Spread Spectrum Clock Compatible
  • Small 7-mm × 7-mm × 0.9-mm 92-Pin Dual Row VQFN Package

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The DS90C187 is a low power Serializer for portable battery powered that reduces the size of the RGB interface between the host GPU and the Display.

The DS90C187 Serializer is designed to support dual pixel data transmission between a Host and a Flat Panel Display at resolutions of up to QXGA (2048x1536) at 60 Hz. The transmitter converts up to 48 bits (Dual Pixel 24-bit color) of 1.8-V LVCMOS data into two channels of 4 data + clock (4D+C) reduced width interface LVDS compatible data streams.

DS90C187 supports 3 modes of operation.

  • In single pixel mode in/out mode, the device can drive up to SXGA+ (1400x1050) at 60 Hz. In this mode, the device converts one bank of 24-bit RGB data to a one channel 4D+C LVDS data stream.
  • In single pixel in / dual pixel out mode, the device can drive up to WUXGA+ (1920x1440) at 60 Hz. In this configuration, the device provides single-to-dual pixel conversion and converts one bank of 24-bit RGB data into two channels of 4D+C LVDS streams at half the pixel clock rate.

In dual pixel in / dual pixel out mode, the device can drive up to QXGA 2048x1536 at 60Hz or up to QSXGA 2560x2048 at 30Hz. In this mode, the device converts 2 channels of 24 bit RGB data into 2 channels of 4D+C LVDS streams. For all the modes, the device supports 18bpp and 24bpp color.

The DS90C187 is offered in a small 92 pin dual row VQFN package and features single 1.8 V supply for minimal power dissipation.

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Similar but not functionally equivalent to the compared device:
DS90C387 ACTIVE +3.3V Dual Pixel LVDS Display Interface (LDI)-SVGA/QXGA Functionally similar to the DS90C187 but has 3.3V IO

Technical documentation

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Type Title Date
* Datasheet DS90C187 Low Power, 1.8-V Dual Pixel FPD-Link (LVDS) Serializer datasheet (Rev. C) Sep. 25, 2018
Application notes High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs Nov. 09, 2018
Technical articles Finding the right pixel clock frequency and throughput for an LVDS display resolution Sep. 26, 2018
Application notes Array QFN Application Note Oct. 31, 2012
User guides C187EKV01 User’s Guide May 03, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

document-generic User guide

The C187EVK01 evaluation module (EVM) helps you evaluate the performance of the DS90C187 low-power 1.8-V dual-pixel FPD-Link LVDS serializer. The device operates off of a single 1.8-V supply and supports input pixel clocks from 50 MHz to 185 MHz (single-in, dual-out) or 25 MHz to 105 MHz (...)

  • 100-mW typical power consumption at 185 MHz (SIDO mode)
  • Drives QXGA and WQXGA class displays
  • Three operating modes:
    • Single pixel in and single pixel out (SISO), 105 MHz (maximum)
    • Single pixel in and dual pixel out (SIDO), 185 MHz
    • Dual pixel in and dual pixel out (DIDO), 105 MHz
  • Supports 24-bit RGB (...)

Design tools & simulation

SNLM112.ZIP (147 KB) - IBIS Model
SPICE-based analog simulation program
TINA-TI TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN-MR (NLA) 92 View options

Ordering & quality

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​


High-speed layout guidelines for reducing EMI in LVDS SerDes designs

This video provides guidelines on how to reduce EMI in designs that use TI serializers and deserializers.

Posted: 13-Jan-2018
Duration: 08:16

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