Product details

Bus voltage (Max) (V) 100 Power switch MOSFET Input VCC (Min) (V) 9 Input VCC (Max) (V) 14 Peak output current (A) 3 Rise time (ns) 8 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 8 Rating Catalog Number of channels (#) 2 Fall time (ns) 8 Prop delay (ns) 22 Iq (uA) 10 Input threshold TTL Channel input logic TTL Negative voltage handling at HS pin (V) -1 Features Driver configuration Dual, Non-Inverting
Bus voltage (Max) (V) 100 Power switch MOSFET Input VCC (Min) (V) 9 Input VCC (Max) (V) 14 Peak output current (A) 3 Rise time (ns) 8 Operating temperature range (C) -40 to 125 Undervoltage lockout (Typ) 8 Rating Catalog Number of channels (#) 2 Fall time (ns) 8 Prop delay (ns) 22 Iq (uA) 10 Input threshold TTL Channel input logic TTL Negative voltage handling at HS pin (V) -1 Features Driver configuration Dual, Non-Inverting
HSOIC (DDA) 8 19 mm² 4.9 x 3.9 HVSSOP (DGN) 8 9 mm² 3 x 3 SOIC (D) 8 19 mm² 4.9 x 3.9 WSON (DPR) 10 16 mm² 4 x 4 WSON (NGT) 8 16 mm² 4 x 4
  • Independent High and Low Driver Logic Inputs
  • Bootstrap Supply Voltage up to 100-V DC
  • Drives Both a High-Side and Low-Side N-Channel MOSFETs
  • Fast Propagation Times (25 ns Typical)
  • Drives 1000-pF Load With 8-ns Rise and Fall Times
  • Excellent Propagation Delay Matching (3 ns Typical)
  • Supply Rail Undervoltage Lockout
  • Low Power Consumption
  • Pin Compatible With HIP2100 and HIP2101
  • Independent High and Low Driver Logic Inputs
  • Bootstrap Supply Voltage up to 100-V DC
  • Drives Both a High-Side and Low-Side N-Channel MOSFETs
  • Fast Propagation Times (25 ns Typical)
  • Drives 1000-pF Load With 8-ns Rise and Fall Times
  • Excellent Propagation Delay Matching (3 ns Typical)
  • Supply Rail Undervoltage Lockout
  • Low Power Consumption
  • Pin Compatible With HIP2100 and HIP2101

The LM25101 high-voltage gate driver is designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half-bridge configuration. The A version provides a full 3-A of gate drive while the B and C versions provide 2-A and 1-A, respectively. The outputs are independently controlled with TTL input thresholds. An integrated high voltage diode is provided to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout is provided on both the low-side and the high-side power rails.

These devices are available in the standard 8-pin SOIC, 8-pin SO-PowerPAD, 8-pin WSON, 10-pin WSON, and 8-pin MSOP PowerPAD packages.

The LM25101 high-voltage gate driver is designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half-bridge configuration. The A version provides a full 3-A of gate drive while the B and C versions provide 2-A and 1-A, respectively. The outputs are independently controlled with TTL input thresholds. An integrated high voltage diode is provided to charge the high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout is provided on both the low-side and the high-side power rails.

These devices are available in the standard 8-pin SOIC, 8-pin SO-PowerPAD, 8-pin WSON, 10-pin WSON, and 8-pin MSOP PowerPAD packages.

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Technical documentation

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Type Title Date
* Data sheet LM25101 3-A, 2-A, and 1-A 80-V Half-Bridge Gate Drivers datasheet (Rev. C) PDF | HTML 28 Sep 2016
Application note Understanding and comparing peak current capability of gate drivers PDF | HTML 30 Mar 2021
Application note External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application note Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Oct 2018
Technical article How to achieve higher system robustness in DC drives, part 3: minimum input pulse 19 Sep 2018
Technical article How to achieve higher system robustness in DC drives, part 2: interlock and deadtime 30 May 2018
Technical article Boosting efficiency for your solar inverter designs 24 May 2018
Technical article How to achieve higher system robustness in DC drives, part 1: negative voltage 17 Apr 2018

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HVSSOP (DGN) 8 View options
SO PowerPAD (DDA) 8 View options
SOIC (D) 8 View options
WSON (DPR) 10 View options
WSON (NGT) 8 View options

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