2-A, 100-V half bridge gate driver with 8-V UVLO and adaptive delay
Product details
Parameters
Package | Pins | Size
Features
- Drives Both a High-Side and Low-Side N-Channel MOSFET
- Adaptive Rising and Falling Edges With Programmable
Additional Delay - Single Input Control
- Bootstrap Supply Voltage Range up to 118-V DC
- Fast Turnoff Propagation Delay (25 ns Typical)
- Drives 1000-pF Loads With 15-ns Rise and Fall Times
- Supply Rail Undervoltage Lockout
- SOIC and WSON-10 4-mm × 4-mm Package
Description
The LM5104 High-Voltage Gate Driver is designed to drive both the high-side and the low-side N-channel MOSFETs in a synchronous buck configuration. The floating high-side driver can work with supply voltages up to 100 V. The high-side and low-side gate drivers are controlled from a single input. Each change in state is controlled in an adaptive manner to prevent shoot-through issues. In addition to the adaptive transition timing, an additional delay time can be added, proportional to an external setting resistor. An integrated high-voltage diode is provided to charge high-side gate drive bootstrap capacitor. A robust level shifter operates at high speed while consuming low power and providing clean level transitions from the control logic to the high-side gate driver. Undervoltage lockout is provided on both the low-side and the high-side power rails. This device is available in the standard SOIC and the WSON packages.
Same functionality but is not pin-for-pin or parametrically equivalent to the compared device:
Technical documentation
| Type | Title | Date | |
|---|---|---|---|
| * | Data sheet | LM5104 High-Voltage Half-Bridge Gate Driver With Adaptive Delay datasheet (Rev. D) | Dec. 16, 2014 |
| Application note | External Gate Resistor Selection Guide (Rev. A) | Feb. 28, 2020 | |
| Application note | Understanding Peak IOH and IOL Currents (Rev. A) | Feb. 28, 2020 | |
| More literature | Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) | Oct. 29, 2018 | |
| Technical article | How to achieve higher system robustness in DC drives, part 3: minimum input pulse | Sep. 19, 2018 | |
| Technical article | How to achieve higher system robustness in DC drives, part 2: interlock and deadtime | May 30, 2018 | |
| Technical article | Boosting efficiency for your solar inverter designs | May 24, 2018 | |
| Technical article | How to achieve higher system robustness in DC drives, part 1: negative voltage | Apr. 17, 2018 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
| Package | Pins | Download |
|---|---|---|
| SOIC (D) | 8 | View options |
| WSON (DPR) | 10 | View options |
Ordering & quality
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- REACH
- Device marking
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- MSL rating/Peak reflow
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- Ongoing reliability monitoring
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