Product details

Features Buffer Frequency (Max) (kHz) 400 VCCA (Min) (V) 2 VCCA (Max) (V) 15 VCCB (Min) (V) 2 VCCB (Max) (V) 15 Supply restrictions VCC Single Supply Rating Catalog Operating temperature range (C) -40 to 85
Features Buffer Frequency (Max) (kHz) 400 VCCA (Min) (V) 2 VCCA (Max) (V) 15 VCCB (Min) (V) 2 VCCB (Max) (V) 15 Supply restrictions VCC Single Supply Rating Catalog Operating temperature range (C) -40 to 85
PDIP (P) 8 93 mm² 9.81 x 9.43 SOIC (D) 8 19 mm² 3.91 x 4.9 TSSOP (PW) 8 19 mm² 3 x 6.4 VSSOP (DGK) 8 15 mm² 3 x 4.9
  • Operating Power-Supply Voltage Range
    of 2 V to 15 V
  • Can Interface Between I2C Buses Operating at
    Different Logic Levels (2 V to 15 V)
  • Longer Cables by allowing bus capacitance of
    400 pF on Main Side (Sx/Sy) and 4000 pF on
    Transmission Side (Tx/Ty)
  • Outputs on the Transmission Side (Tx/Ty) Have
    High Current Sink Capability for Driving Low-
    Impedance or High-Capacitive Buses
  • Interface With Optoelectrical Isolators and Similar
    Devices That Need Unidirectional Input and
    Output Signal Paths by Splitting I2C Bus Signals
    Into Pairs of Forward (Tx/Ty) and Reverse (Rx/Ry)
    Signals
  • 400-kHz Fast I2C Bus Operation Over at Least
    20 Meters of Wire
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
  • Operating Power-Supply Voltage Range
    of 2 V to 15 V
  • Can Interface Between I2C Buses Operating at
    Different Logic Levels (2 V to 15 V)
  • Longer Cables by allowing bus capacitance of
    400 pF on Main Side (Sx/Sy) and 4000 pF on
    Transmission Side (Tx/Ty)
  • Outputs on the Transmission Side (Tx/Ty) Have
    High Current Sink Capability for Driving Low-
    Impedance or High-Capacitive Buses
  • Interface With Optoelectrical Isolators and Similar
    Devices That Need Unidirectional Input and
    Output Signal Paths by Splitting I2C Bus Signals
    Into Pairs of Forward (Tx/Ty) and Reverse (Rx/Ry)
    Signals
  • 400-kHz Fast I2C Bus Operation Over at Least
    20 Meters of Wire
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22

The P82B96 device is a bus buffer that supports bidirectional data transfer between an I2C bus and a range of other bus configurations with different voltage and current levels.

One of the advantages of the P82B96 is that it supports longer cables/traces and allows for more devices per I2C bus because it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I2C nodes are not apparent to other I2C buses (or nodes). The restrictions on the number of I2C devices in a system due to capacitance, or the physical separation between them, are greatly improved.

The device is able to provide galvanic isolation (optocoupling) or use balanced transmission lines (twisted pairs), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected directly (without causing bus latching), to provide an bidirectional signal line with I2C properties (open-drain driver). Likewise, the Ty and Ry signals may also be connected together to provide an bidirectional signal line with I2C properties (open-drain driver). This allows for a simple communication design, saving design time and costs.

Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does not support this configuration. Bidirectional I2C signals do not have a direction control pin so, instead, slightly different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I2C low applied at the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard I2C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation.

The Sx/Sy side of the P82B96 is intended for I2C logic voltage levels of I2C master and slave devices or Tx/Rx signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.

In any design, the Sx pins of different devices should never be linked, because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes.

The P82B96 device is a bus buffer that supports bidirectional data transfer between an I2C bus and a range of other bus configurations with different voltage and current levels.

One of the advantages of the P82B96 is that it supports longer cables/traces and allows for more devices per I2C bus because it can isolate bus capacitance such that the total loading (devices and trace lengths) of the new bus or remote I2C nodes are not apparent to other I2C buses (or nodes). The restrictions on the number of I2C devices in a system due to capacitance, or the physical separation between them, are greatly improved.

The device is able to provide galvanic isolation (optocoupling) or use balanced transmission lines (twisted pairs), because separate directional Tx and Rx signals are provided. The Tx and Rx signals may be connected directly (without causing bus latching), to provide an bidirectional signal line with I2C properties (open-drain driver). Likewise, the Ty and Ry signals may also be connected together to provide an bidirectional signal line with I2C properties (open-drain driver). This allows for a simple communication design, saving design time and costs.

Two or more Sx or Sy I/Os must not be connected to each other on the same node. The P82B96 design does not support this configuration. Bidirectional I2C signals do not have a direction control pin so, instead, slightly different logic low-voltage levels are used at Sx/Sy to avoid latching of this buffer. A standard I2C low applied at the Rx/Ry of a P82B96 is propagated to Sx/Sy as a buffered low with a slightly higher voltage level. If this special buffered low is applied to the Sx/Sy of another P82B96, the second P82B96 does not recognize it as a standard I2C bus low and does not propagate it to its Tx/Ty output. The Sx/Sy side of P82B96 may not be connected to similar buffers that rely on special logic thresholds for their operation.

The Sx/Sy side of the P82B96 is intended for I2C logic voltage levels of I2C master and slave devices or Tx/Rx signals of a second P82B96, if required. If Rx and Tx are connected, Sx can function as either the SDA or SCL line. Similarly, if Ry and Ty are connected, Sy can function as either the SDA or SCL line. There are no restrictions on the interconnection of the Tx/Rx and Ty/Ry I/O pins to other P82B96s, for example in a star or multi-point configuration (multiple P82B96 devices share the same Tx/Rx and Ty/Ry nodes) with the Tx/Rx and Ty/Ry I/O pins on the common bus, and the Sx/Sy side connected to the line-card slave devices.

In any design, the Sx pins of different devices should never be linked, because the resulting system would be very susceptible to induced noise and would not support all I2C operating modes.

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Technical documentation

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Type Title Date
* Data sheet P82B96 I2C Compatible Dual Bidirectional Bus Buffer datasheet (Rev. C) 14 May 2017
Design guide I2C Range Extension: I2C with CAN 07 Jan 2019
Application note Choosing the Correct I2C Device for New Designs 07 Sep 2016
Selection guide I2C Infographic Flyer 03 Dec 2015
Application note Understanding the I2C Bus 30 Jun 2015
Application note Maximum Clock Frequency of I2C Bus Using Repeaters 15 May 2015
Application note I2C Bus Pull-Up Resistor Calculation 13 Feb 2015

Design & development

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Package Pins Download
PDIP (P) 8 View options
SOIC (D) 8 View options
TSSOP (PW) 8 View options
VSSOP (DGK) 8 View options

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