The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 12 Gbps and compensates for losses due to board traces and cables.
The device is transparent to DisplayPort (DP) link training such a way that a DP source and a sink can perform effective link training overcoming traditional “aux snooping” re-drivers’ shortcomings. Additionally, the device is position independent. It can be placed inside source, cable or sink effectively providing a “negative loss” component to the overall link budget. Linear equalization inside SN65DP141 also increases link margin when used with a receiver implementing Decision Feedback Equalization (DFE).
SN65DP141 allows independent channel control for equalization, gain, dynamic range using both I2C and GPIO configurations.
|Part number||Order||ESD HBM (kV)||Protocols||Speed (Max) (Gbps)||Supply voltage (V)||Number of TMDS outputs||Package Group||Package size: mm2:W x L (PKG)||Operating temperature range (C)|
|0||WQFN | 38||38WQFN: 35 mm2: 5 x 7 (WQFN | 38)||-40 to 85|
||11||DisplayPort||2.7||3.3||0||VQFN | 36||36VQFN: 36 mm2: 6 x 6 (VQFN | 36)||0 to 85|
||2||HDMI||5.4||3.3||1||WQFN | 56||56WQFN: 55 mm2: 5 x 11 (WQFN | 56)||0 to 85|
||2||DisplayPort||5.4||3.3||0||VQFN | 48||48VQFN: 49 mm2: 7 x 7 (VQFN | 48)||0 to 85|