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Product details

Parameters

Technology Family AUP VCC (Min) (V) 0.8 VCC (Max) (V) 3.6 Channels (#) 1 Inputs per channel 2 IOL (Max) (mA) 4 IOH (Max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Partial Power Down (Ioff), Over-Voltage Tolerant Inputs, Very High Speed (tpd 5-10ns) Data rate (Max) (Mbps) 100 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other AND gate

Package | Pins | Size

DSBGA (YFP) 6 1 mm² .8 x 1.2 DSBGA (YZP) 5 2 mm² .928 x 1.428 SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-5X3 (DRL) 5 3 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1 USON (DRY) 6 1 mm² 1.5 x 1 X2SON (DPW) 5 1 mm² .8 x .8 X2SON (DSF) 6 1 mm² 1 x 1 open-in-new Find other AND gate

Features

  • Available in the Ultra Small 0.64 mm2 Package
    (DPW) With 0.5-mm Pitch
  • Low Static-Power Consumption:
    ICC = 0.9 µA Maximum
  • Low Dynamic-Power Consumption:
    Cpd = 4.3 pF Typical at 3.3 V
  • Low Input Capacitance: Ci = 1.5 pF Typical
  • Low Noise: Overshoot and Undershoot
    <10% of VCC
  • Ioff Supports Live Insertion, Partial-Power-Down
    Mode, and Back Drive Protection
  • Schmitt-Trigger Action Allows Slow Input
    Transition and Better Switching Noise Immunity at
    the Input (Vhys = 250 mV Typical at 3.3 V)
  • Wide Operating VCC Range of 0.8 V to 3.6 V
  • Optimized for 3.3-V Operation
  • 3.6-V I/O Tolerant to Support Mixed-Mode Signal
    Operation
  • tpd = 4.3 ns Maximum at 3.3 V
  • Suitable for Point-to-Point Applications
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
open-in-new Find other AND gate

Description

This single 2-input positive-AND gate is designed for 0.8-V to 3.6-V VCC operation and performs the Boolean function Y = A • B or Y = A\ + B\ in positive logic.

open-in-new Find other AND gate
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet SN74AUP1G08 Low-Power Single 2-Input Positive-AND Gate datasheet (Rev. P) Jun. 17, 2016
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Application note Designing and Manufacturing with TI's X2SON Packages Aug. 23, 2017
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Understanding Schmitt Triggers Sep. 21, 2011
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCEM405A.ZIP (65 KB) - IBIS Model
SIMULATION MODEL Download
SCEM690.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
DSBGA (YFP) 6 View options
DSBGA (YZP) 5 View options
SC70 (DCK) 5 View options
SON (DRY) 6 View options
SON (DSF) 6 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options
X2SON (DPW) 5 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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