Home Switches & multiplexers Analog switches & muxes
Home
Switches & multiplexers
Analog switches & muxes

SN74LVC2G53

ACTIVE

5-V, 2:1 (SPDT), 1-channel general-purpose analog switch (available in the NanoFree™ package)

Order now
Data sheet

SN74LVC2G53

ACTIVE
Data sheet Order now

Product details

Configuration 2:1 SPDT Number of channels (#) 1 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (Typ) (Ohms) 6.5 CON (Typ) (pF) 19.5 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (C) -40 to 85 Input/output continuous current (Max) (mA) 50 Rating Catalog Supply current (Typ) (uA) 1
Configuration 2:1 SPDT Number of channels (#) 1 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Protocols Analog Ron (Typ) (Ohms) 6.5 CON (Typ) (pF) 19.5 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 300 Operating temperature range (C) -40 to 85 Input/output continuous current (Max) (mA) 50 Rating Catalog Supply current (Typ) (uA) 1
DSBGA (YZP) 8 3 mm² .928 x 1.928 SSOP (DCT) 8 8 mm² 2.95 x 2.80 VSSOP (DCU) 8 6 mm² 2 x 3.1
  • Available in the Texas Instruments
    NanoFree™ Package
  • 1.65-V to 5.5-V VCC Operation
  • High On-Off Output Voltage Ratio
  • High Degree of Linearity
  • High Speed, Typically 0.5 ns (VCC = 3 V,
    CL = 50 pF)
  • Low ON-State Resistance, Typically 6.5 Ω
    (VCC = 4.5 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • Available in the Texas Instruments
    NanoFree™ Package
  • 1.65-V to 5.5-V VCC Operation
  • High On-Off Output Voltage Ratio
  • High Degree of Linearity
  • High Speed, Typically 0.5 ns (VCC = 3 V,
    CL = 50 pF)
  • Low ON-State Resistance, Typically 6.5 Ω
    (VCC = 4.5 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II

This single 2:1 analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G53 device can handle both analog and digital signals. This device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

This single 2:1 analog multiplexer/demultiplexer is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G53 device can handle both analog and digital signals. This device permits signals with amplitudes of up to 5.5 V (peak) to be transmitted in either direction.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.
open-in-new Find other Analog switches & muxes
Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 31
Type Title Date
* Data sheet SN74LVC2G53 Single-Pole Double-Throw (SPDT) Analog Switch 2:1 Analog Multiplexer/Demultiplexer datasheet (Rev. Q) PDF | HTML 10 Jan 2019
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 02 Jun 2022
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 01 Dec 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
More literature SN74LVC1G3157 and SNS74LVC2G53 SPDT Analog Switches 12 Jun 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

DIP-ADAPTER-EVM — DIP adapter evaluation module

Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and inexpensive way to interface with small, surface-mount ICs. You can connect any supported op amp using the included Samtec terminal strips or wire them directly to existing circuits.

The (...)

document-pdfAcrobat User guide
Not available on TI.com
Evaluation board

TL16C750EEVM — TL16C750E 128-byte FIFO fractional baudrate UART evaluation module

This EVM provides the user with the ability to evaluate the TL16C750E device and its features. The EVM includes an onboard 3.3-V LDO as well as level translation for processors which operate at a higher voltage rail.
Not available on TI.com
Interface adapter

LEADED-ADAPTER1 — Surface mount to DIP header adapter for quick testing of TI's 5, 8, 10, 16 & 24-pin leaded packages

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Not available on TI.com
Interface adapter

LEADLESS-ADAPTER1 — Surface mount to DIP header adapter for testing of TI's 6,8,10,12,14,16, & 20-pin leadless packages

The EVM-LEADLESS1 board allows for quick testing and bread boarding of TI's common leadless packages.  The board has footprints to convert TI's DRC, DTP, DQE, RBW, RGY, RSE, RSV, RSW RTE, RTJ, RUK , RUC, RUG, RUM,RUT and YZP surface mount packages to 100mil DIP headers.
Not available on TI.com
Simulation model

SN74LVC2G53 IBIS Model

SCEM481.ZIP (99 KB) - IBIS Model
Download
Reference designs

TIDA-01022 — Flexible 3.2-GSPS multi-channel AFE reference design for DSOs, radar and 5G wireless test systems

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
document-pdfAcrobat Schematic
Reference designs

TIDA-010122 — Reference design synchronizing data converter DDC and NCO features for multi-channel RF systems

This reference design addresses synchronization design challenges associated with emerging 5G adapted applications like massive multiple input multiple output (mMIMO), phase array radar and communication payload. The typical RF front end contains antenna, low-noise amplifier (LNA), mixer, local (...)
document-pdfAcrobat Schematic
Reference designs

TIDA-010128 — Scalable 20.8 GSPS reference design for 12 bit digitizers

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
document-pdfAcrobat Schematic
Reference designs

TIDA-01028 — 12.8-GSPS analog front end reference design for high-speed oscilloscope and wide-band digitizer

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
document-pdfAcrobat Schematic
Reference designs

TIDA-01027 — Low-noise power supply reference design maximizing performance in 12.8-GSPS data acquisition systems

This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
document-pdfAcrobat Schematic
Reference designs

TIDA-010131 — Multichannel RF transceiver clocking reference design for RADARs and wireless 5G testers

Analog front end for high-speed end equipments like phased-array radars, wireless communication testers, and electronic warfare require synchronized, multipletransceiver signal chains. Each transceiver signal chain includes high-speed, analog-to-digital converters (ADCs), digital-to-analog (...)
document-generic Schematic
Reference designs

TIDA-01024 — High Channel Count JESD204B Daisy Chain Clock Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports scaling up JESD204B synchronized clocks in daisy chain configuration. This (...)
document-pdfAcrobat Schematic
Reference designs

TIDA-01023 — High Channel Count JESD204B Clock Generation Reference Design for RADAR and 5G Wireless Testers

High-speed multi-channel applications require low noise and scalable clocking solutions capable of precise channel-to-channel skew adjustment to achieve optimal system SNR, SFDR, and ENOB. This reference design supports high channel count JESD204B synchronized clocks using one master and multiple (...)
document-pdfAcrobat Schematic
Package Pins Download
DSBGA (YZP) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

View all forum topics

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos