Product details

Operating temperature range (C) -40 to 85
Operating temperature range (C) -40 to 85
HVQFP (RCP) 64 144 mm² 12 x 12
  • Hot Plug Protection
  • 0.6 to 1.5 Gigabits Per Second (Gbps) Serializer/Deserializer
  • High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD™)
  • 2.5 V Power Supply for Low Power Operation
  • Programmable Voltage Output Swing on Serial Output
  • Interfaces to Backplane, Copper Cables, or Optical Converters
  • Rated for Industrial Temperature Range
  • On-Chip 8-Bit/10-Bit (8B/10B) Encoding/Decoding, Comma Alignment, and Link Synchronization
  • On-Chip PLL Provides Clock Synthesis From Low-Speed Reference
  • Receiver Differential Input Thresholds 200 mV Minimum
  • Typical Power: 250 mW
  • Loss of Signal (LOS) Detection
  • Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link

PowerPAD is a trademark of Texas Instruments.

  • Hot Plug Protection
  • 0.6 to 1.5 Gigabits Per Second (Gbps) Serializer/Deserializer
  • High-Performance 64-Pin VQFP Thermally Enhanced Package (PowerPAD™)
  • 2.5 V Power Supply for Low Power Operation
  • Programmable Voltage Output Swing on Serial Output
  • Interfaces to Backplane, Copper Cables, or Optical Converters
  • Rated for Industrial Temperature Range
  • On-Chip 8-Bit/10-Bit (8B/10B) Encoding/Decoding, Comma Alignment, and Link Synchronization
  • On-Chip PLL Provides Clock Synthesis From Low-Speed Reference
  • Receiver Differential Input Thresholds 200 mV Minimum
  • Typical Power: 250 mW
  • Loss of Signal (LOS) Detection
  • Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link

PowerPAD is a trademark of Texas Instruments.

The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the TLK2501, a 1.6 to 2.5 Gbps transceiver, and the TLK3101, a 2.5 to 3.125 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future.

The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency).

The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board.

The TLK1501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface.

The TLK1501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals during power up as well as DOUTTXP and DOUTTXN in a high-impedance state.

The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

To prevent a data bit error from causing a valid data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK1501.

The TLK1501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a transmit-only mode, since the receiver is not tracking the data.

The TLK1501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK1501 is characterized for operation from –40°C to 85°C.

The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the TLK2501, a 1.6 to 2.5 Gbps transceiver, and the TLK3101, a 2.5 to 3.125 Gbps transceiver, providing a wide range of performance solutions with no required board layout changes.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future.

The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency).

The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board.

The TLK1501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface.

The TLK1501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low during power up. This circuit also holds the parallel side output signal terminals during power up as well as DOUTTXP and DOUTTXN in a high-impedance state.

The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

To prevent a data bit error from causing a valid data packet from being interpreted as a comma and thus causing the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off after the link is properly established in TLK1501.

The TLK1501 allows users to implement redundant ports by connecting receive data bus terminals from two TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a transmit-only mode, since the receiver is not tracking the data.

The TLK1501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power-efficient, consuming less than 360 mW typically. The TLK1501 is characterized for operation from –40°C to 85°C.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 6
Type Title Date
* Data sheet 0.6 to 1.5 Gbps Transceiver datasheet (Rev. F) 05 Sep 2003
Technical article Get Connected: SerDes demystified 08 May 2014
Application note Using TI's CDCV304 w/Backplane Transceiver (TLK1201/1501/2201/2501/2701/3101) (Rev. A) 20 Apr 2006
Application note Using TI's CDCVF2310 and CDCVF25081 with TLK1501 Serial Transceiver 14 May 2003
Application note Interfacing Between LVPECL, VML, CML and LVDS Levels 17 Dec 2002
EVM User's guide TLK1501 Serdes EVM Kit Setup and Usage User's Guide 14 Jun 2000

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TLK1501EVM — TLK1501 SerDes Evaluation Module

The TLK1501 serdes evaluatiom module (EVM) board is used to evaluate the TLK1501 device (VQFP) and associated optical interface (NetLight™) for point-to-point data transmission applications.

The board enables the designer to connect 50 ohm parallel buses to both transmitter and receiver connectors. (...)

Not available on TI.com
Simulation tool

PSPICE-FOR-TI PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Package Pins Download
HVQFP (RCP) 64 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos