TPD4S009
- IEC 61000-4-2 Level 4 ESD Protection
- ±8-kV Contact Discharge
- IEC 61000-4-5 Surge Protection
- 2.5A (8/20µs)
- I/O Capacitance: 0.8 pF (Typical)
- Low Leakage Current: 10 nA (Typical)
- Supports High-Speed Differential Data Rates
(3-dB Bandwidth > 4 GHz) - Ultra-low Matching Capacitance Between
Differential Signal Pairs - Ioff Feature for the TPD4S009
- Industrial Temperature Range:
–40°C to 85°C - Easy Straight through Routing, Space-Saving
Package Options
The TPD4S009 and TPD4S010 are four-channel TVS diode arrays for electrostatic discharge (ESD) protection. TPD4S009 and TPD4S010 are rated to dissipate contact ESD strikes at the maximum level specified in the IEC 61000-4-2 international standard (Level 4), with ±8-kV contact discharge ESD protection. The low capacitance (0.8-pF) of these devices, coupled with the excellent matching between differential signal pairs (0.05-pF line-line capacitance for the TPD4S009DRY) enables this device to provide transient voltage suppression circuit protection for high-speed differential data rates (3-dB bandwidth > 4 GHz).
The TPD4S009 is offered in DBV, DCK, DGS, and DRY packages. The TPD4S009DRYR is the most space saving package option available for dual pair high-speed differential lines. The TPD4S010 is offered in the industry standard DQA package. The TPD4S009DGSR and TPD4S010DQAR offer flow-through board layout options to reduce signal glitches normally caused by routing mismatches between the D+ and D signal pair. See also TPD4E05U06DQAR which is P2P compatible with TPD4S010DQAR. This device offers higher IEC ESD protection, lower capacitance, lower RDYN, lower DC breakdown voltage, and lower clamping voltage.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | TPD4S009 4-Channel ESD Solution for High-Speed Differential Interface datasheet (Rev. G) | PDF | HTML | 26 Jun 2015 |
Application note | ESD and Surge Protection for USB Interfaces (Rev. B) | PDF | HTML | 11 Jan 2024 | |
Application brief | ESD Protection for HDMI Applications (Rev. A) | PDF | HTML | 01 Nov 2023 | |
Selection guide | System-Level ESD Protection Guide (Rev. D) | 07 Sep 2022 | ||
Application note | ESD Packaging and Layout Guide (Rev. B) | PDF | HTML | 18 Aug 2022 | |
White paper | Designing USB for short-to-battery tolerance in automotive environments | 10 Feb 2016 | ||
Analog Design Journal | Design Considerations for System-Level ESD Circuit Protection | 25 Sep 2012 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
ESDEVM — ESD evaluation module
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
TINA-TI — SPICE-based analog simulation program
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Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
SOT-23 (DBV) | 6 | Ultra Librarian |
SOT-SC70 (DCK) | 6 | Ultra Librarian |
USON (DRY) | 6 | Ultra Librarian |
VSSOP (DGS) | 10 | Ultra Librarian |
Ordering & quality
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