GUI für Evaluierungsmodul (EVM)
SCAC100 — CDCE72010EVM Control GUI
Unterstützte Produkte und Hardware
Produkte
Taktgeneratoren
- CDCE72010 — Jitterarmer Taktsynchronisation und Jitter-Cleaner mit 10 Ausgängen
CDCE72010
Jitterarmer Taktsynchronisation und Jitter-Cleaner mit 10 Ausgängen
Datenblatt
CDCE72010
- High Performance LVPECL, LVDS, LVCMOS PLL Clock Synchronizer
- Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy
Support with Manual or Automatic Selection - Accepts Two Differential Input (LVPECL or LVDS) References up to 500MHz
(or Two LVCMOS Inputs up to 250MHz) as PLL Reference - VCXO_IN Clock is Synchronized to One of Two Reference Clocks
- VCXO_IN Frequencies up to 1.5GHz (LVPECL)
800MHz for LVDS and
250MHz for LVCMOS Level Signaling - Outputs Can be a Combination of LVPECL, LVDS, and LVCMOS
(Up to 10 Differential LVPECL or LVDS Outputs or up to
20 LVCMOS Outputs), Output 9 can be Converted to an
Auxiliary Input as a 2nd VC(X)O. - Output Divider is Selectable to Divide by 1, 2, 3, 4, 5, 6, 8, 10,
12, 16, 18, 20, 24, 28, 30, 32, 36, 40, 42, 48, 50, 56, 60, 64, 70,
or 80 On Each Output Individually up to Eight Dividers. (Except for
Output 0 and 9, Output 0 Follows Output 1 Divider and Output 9
Follows Output 8 Divider) - SPI Controllable Device Setting
- Individual Output Enable Control via SPI Interface
- Integrated On-Chip Non-Volatile Memory (EEPROM) to Store Settings
without the Need to Apply High Voltage to the Device - Optional Configuration Pins to Select Between Two Default Settings
Stored in EEPROM - Efficient Jitter Cleaning from Low PLL Loop Bandwidth
- Very Low Phase Noise PLL Core
- Programmable Phase Offset (Input Reference to Outputs)
- Wide Charge-Pump Current Range From 200µA to 3mA
- Presets Charge-Pump to VCC_CP/2 for Fast Center-Frequency
Setting of VC(X)O, Controlled Via the SPI Bus - SERDES Startup Mode (Depending on VCXO Range)
- Auxiliary Input: Output 9 can Serve as 2nd VCXO Input to Drive
All Outputs or to Serve as PLL Feedback Signal - RESET or HOLD Input Pin to Serve as Reset or Hold Functions
- REFERENCE SELECT for Manual Select Between Primary and Secondary
Reference Clocks - POWER DOWN (PD) to Put Device in Standby Mode
- Analog and Digital PLL Lock Indicator
- Internally Generated VBB Bias Voltages for Single-Ended Input Signals
- Frequency Hold-Over Mode Activated by HOLD Pin or SPI Bus to Improve
Fail-Safe Operation - Input to All Outputs Skew Control
- Individual Skew Control for Each Output with Each Output Divider
- Packaged in a QFN-64 Package
- ESD Protection Exceeds 2kV HBM
- Industrial Temperature Range of –40°C to 85°
The CDCE72010 is a high-performance, low phase noise, and low skew clock synchronizer that synchronizes a VCXO (Voltage Controlled Crystal Oscillator) or VCO (Voltage Controlled Oscillator) frequency to one of two reference clocks. The clock path is fully programmable providing the user with a high degree of flexibility. The following relationship applies to the dividers:
Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)
The VC(X)O_IN clock operates up to 1.5GHz through the selection of external VC(X)O and loop filter components. The PLL loop bandwidth and damping factor can be adjusted to meet different system requirements.
The CDCE72010 can lock to one of two reference clock inputs (PRI_REF and SEC_REF) and supports frequency hold-over mode for fail-safe and system redundancy. The outputs of the CDCE72010 are user definable and can be any combination of up to 10 LVPECL/LVDS outputs or up to 20 LVCMOS outputs. The built-in synchronization latches ensure that all outputs are synchronized for very low output skew.
All device settings, including output signaling, divider value selection, input selection, and many more, are programmable with the SPI (4-wire Serial Peripheral Interface). The SPI allows individual control of the device settings.
The device operates in a 3.3V environment and is characterized for operation from –40°C to +85°C.
The CDCE72010 is available in a 64-pin lead-free “green” plastic quad flatpack package with enhanced bottom thermal pad for heat dissipation. The Texas Instruments package designator is RGC (S-PQFP-N64).
Technische Dokumentation
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Alle anzeigen 12 | Typ | Titel | Datum | ||
|---|---|---|---|---|
| * | Data sheet | Ten Output High Performance Clock Synchronizer, Jitter Cleaner &Clock Distrib datasheet (Rev. C) | 31 Jan 2012 | |
| Analog Design Journal | Q3 2009 Issue Analog Applications Journal | 24 Sep 2018 | ||
| User guide | ADS42B4x - User's Guide (Rev. A) | 30 Jan 2015 | ||
| User guide | TSW3725 Evaluation Module | 25 Okt 2011 | ||
| Analog Design Journal | 3Q 2011 Issue Analog Applications Journal | 16 Sep 2011 | ||
| Application note | Clock jitter analyzed in the time domain, Part 3 | 16 Sep 2011 | ||
| Analog Design Journal | 4Q 2010 Issue Analog Applications Journal | 15 Nov 2010 | ||
| Analog Design Journal | Clock jitter analyzed in the time domain, Part 2 | 15 Nov 2010 | ||
| Analog Design Journal | Impact of sampling-clock spurs on ADC performance | 14 Jul 2009 | ||
| Application note | CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters | 08 Jun 2008 | ||
| Application note | Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 | 02 Jun 2008 | ||
| Application note | Using the CDCE72010 as a Frequency Synthesizer | 31 Mai 2008 |
Design und Entwicklung
Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.
Evaluierungsplatine
ADS4122EVM — ADS4122 12 Bit, 65 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS4122EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4122 device, an extremely low power 12-bit 65 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible (...)
Evaluierungsplatine
ADS4129EVM — ADS4129 12 Bit, 250 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS4129EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' ADS4129 device, an extremely low power 12-bit 250 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible environment to (...)
Evaluierungsplatine
ADS4142EVM — ADS4142 14 Bit, 65 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS4142EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4142 device, an extremely low power 14-bit 65 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a flexible (...)
Evaluierungsplatine
ADS41B25EVM — ADS41B25 12 Bit, 125 MSPS, Analog-zu-Digital-Wandler-Evaluierungsmodul
The ADS41B25EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS41B25 device, an extremely low power 12-bit 125 MSPS analog to digital converter with integrated high-impedance input buffer. The ADC features a configurable parallel DDR LVDS or CMOS (...)
Evaluierungsplatine
ADS41B29EVM — ADS41B29 12 Bit, 250 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS41B29EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS41B29 device, an extremely low power 12-bit 250 MSPS analog to digital converter with integrated high-impedance input buffer. The ADC features a configurable parallel DDR LVDS or CMOS (...)
Evaluierungsplatine
ADS4222EVM — ADS4222 12 Bit, 65 MSPS, Analog-zu-Digital-Wandler mit 2 Kanälen – Evaluierungsmodul
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS4225EVM — ADS4225 12 Bit, 125 MSPS, Analog-zu-Digital-Wandler mit 2 Kanälen – Evaluierungsmodul
The ADS4225EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4225 device, an extremely low power dual channel 12-bit 125 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS4229EVM — ADS4229 Zweikanal, 12 Bit, 250 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS4242EVM — ADS4242 Zweikanal, 14 Bit, 65 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS4242EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4242 device, an extremely low power dual channel 14-bit 65 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS4245EVM — ADS4245 Zweikanal, 14 Bit, 125 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS4245EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4245 device, an extremely low power dual channel 14-bit 125 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS4249EVM — ADS4249 Zweikanal, 14 Bit, 250 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS4249EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments‘ ADS4249 device, an extremely low power dual channel 14-bit 250 MSPS analog to digital converter. The ADC features a configurable parallel DDR LVDS or CMOS outputs. The EVM provides a (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS5482EVM — ADS5482 16 Bit, 105 MSPS, Analog-zu-Digital-Wandler-Evaluierungsmodul
Der ADS5482EVM ist eine Platine, die es dem Entwickler ermöglicht, den ADS5482-Baustein von Texas Instruments, einen 16-Bit-ADC mit 105 MSPS und DDR-LVDS-Ausgängen, zu evaluieren. Mit der mitgelieferten Breakout-Platine für den Logikanalysator kann der LVDS-Ausgang des ADC direkt mit dem (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS5484EVM — ADS5484 16 Bit, 170 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
Der ADS5484EVM ist eine Platine, die es dem Entwickler ermöglicht, den ADS5484-Baustein von Texas Instruments, einen 16-Bit-ADC mit 170 MSPS und DDR-LVDS-Ausgängen, zu evaluieren. Mit der mitgelieferten Breakout-Platine für den Logikanalysator kann der LVDS-Ausgang des ADC direkt mit dem (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
ADS58C28EVM — ADS58C28 Zweikanal, 11 Bit, 200 MSPS, Analog-zu-Digital-Wandler – Evaluierungsmodul
The ADS58C28EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' ADS58C28 device, a dual channel 11-bit 200 MSPS analog to digital converter featuring TI's SNRBoost technology. The ADC EVM features a DDR LVDS data output which is compatible with TI's (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
DAC5688EVM — DAC5688-Evaluierungsmodul
The DAC5688EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x/8x interpolation filters, on-board clock multiplier and PLL, 32-bit NCO and (...)
Benutzerhandbuch: PDF
Evaluierungsplatine
TSW3085EVM — Evaluierungsplatine und Referenzdesign für Breitband-Übertragungssignalkette
The TSW3085 Evalutaion Module is a circuit board that allows system designers to evaluate the combined performance of Texas Instruments' transmit signal chain with the LMK04806B (formally National Semiconductor) low noise clock generator/jitter cleaner. For ease of use as a complete RF transmit (...)
Benutzerhandbuch: PDF
Berechnungstool
SCAC104 — CDCE72010 PLL Loop Filter Calculator
Unterstützte Produkte und Hardware
Produkte
Taktgeneratoren
- CDCE72010 — Jitterarmer Taktsynchronisation und Jitter-Cleaner mit 10 Ausgängen
Simulationstool
PSPICE-FOR-TI — PSpice® für TI Design-und Simulationstool
PSpice® für TI ist eine Design- und Simulationsumgebung, welche Sie dabei unterstützt, die Funktionalität analoger Schaltungen zu evaluieren. Diese Design- und Simulationssuite mit vollem Funktionsumfang verwendet eine analoge Analyse-Engine von Cadence®. PSpice für TI ist kostenlos erhältlich und (...)
| Gehäuse | Pins | CAD-Symbole, Footprints und 3D-Modelle |
|---|---|---|
| VQFN (RGC) | 64 | Ultra Librarian |
Bestellen & Qualität
Beinhaltete Information:
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- MSL-Rating / Spitzenrückfluss
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- Materialinhalt
- Qualifikationszusammenfassung
- Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
- Werksstandort
- Montagestandort
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