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TPIC6B596

AKTIV

8-Bit-Schieberegister für verbesserte Kaskadierung

Eine neuere Version dieses Produkts ist verfügbar

Selbe Funktionalität wie der verglichene Baustein bei abweichender Anschlussbelegung
TLC6C598-Q1 AKTIV Power-Logic- 8-Bit-Schieberegister-LED-Treiber für Fahrzeuganwendungen Same output channel with smaller footprint and support lower supply voltage

Produktdetails

Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 50 Features Enable/Shutdown, Thermal shutdown
Number of channels 8 Topology Open drain Rating Automotive Operating temperature range (°C) -40 to 125 Vin (min) (V) 4.5 Vin (max) (V) 5.5 Vout (max) (V) 50 Features Enable/Shutdown, Thermal shutdown
PDIP (N) 20 228.702 mm² 24.33 x 9.4 SOIC (DW) 20 131.84 mm² 12.8 x 10.3
  • Low rDS(on): 5Ω
  • Avalanche energy: 30mJ
  • Eight power DMOS-transistor outputs of 150-mA continuous current
  • 500mA typical current-limiting capability
  • Output clamp voltage: 50V
  • Enhanced cascading for multiple stages
  • All registers cleared with single input
  • Low power consumption
  • Low rDS(on): 5Ω
  • Avalanche energy: 30mJ
  • Eight power DMOS-transistor outputs of 150-mA continuous current
  • 500mA typical current-limiting capability
  • Output clamp voltage: 50V
  • Enhanced cascading for multiple stages
  • All registers cleared with single input
  • Low power consumption

The TPIC6B596 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium- current or high-voltage loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift- register clear (SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS- transistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50V and 150mA continuous sink- current capability. Each output provides a 500mA typical current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection.

The TPIC6B596 is characterized for operation over the operating case temperature range of −40°C to 125°C.

The TPIC6B596 is a monolithic, high-voltage, medium-current power 8-bit shift register designed for use in systems that require relatively high load power. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other medium- current or high-voltage loads.

This device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage registers on the rising edge of the shift-register clock (SRCK) and the register clock (RCK), respectively. The storage register transfers data to the output buffer when shift- register clear (SRCLR) is high. Write data and read data are valid only when RCK is low. When SRCLR is low, all registers in the device are cleared. When output enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held low, data from the storage register is transparent to the output buffers. When data in the output buffers is low, the DMOS- transistor outputs are off. When data is high, the DMOS-transistor outputs have sink-current capability. The serial output (SER OUT) is clocked out of the device on the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved performance for applications where clock signals may be skewed, devices are not located near one another, or the system must tolerate electromagnetic interference.

Outputs are low-side, open-drain DMOS transistors with output ratings of 50V and 150mA continuous sink- current capability. Each output provides a 500mA typical current limit at TC = 25°C. The current limit decreases as the junction temperature increases for additional device protection.

The TPIC6B596 is characterized for operation over the operating case temperature range of −40°C to 125°C.

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* Data sheet TPIC6B596 Power Logic 8-Bit Shift Register datasheet (Rev. B) PDF | HTML 11 Mär 2025

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