CD4086B-MIL

ACTIVO

Puerta AND OR INVERT con CMOS expandible de doble entrada y ancho 4

Haga su pedido ahora

Hoja de datos

document-pdfAcrobat CD4086B TYPES datasheet (Rev. C) (Inglés)

CD4086B-MIL

ACTIVO

Hoja de datos

Haga su pedido ahora

Detalles del producto

Technology family

CD4000

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

1.5

IOH (max) (mA)

-1.5

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Military

Operating temperature range (°C)

-55 to 125

Technology family

CD4000

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

1.5

IOH (max) (mA)

-1.5

Input type

Standard CMOS

Output type

Push-Pull

Features

Standard speed (tpd > 50ns)

Data rate (max) (Mbps)

8

Rating

Military

Operating temperature range (°C)

-55 to 125

CDIP (J)

14

130.4652 mm² (— mm × — mm)

Medium-speed operation - t_PHL = 90 ns; t_PLH = 140 ns (typ.) at 10 V
INHIBIT and ENABLE inputs
Buffered outputs
100% tested for quiescent current at 20 V
Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
    1 V at V_DD = 5 V
    2 V at V_DD = 10 V
    2.5 V at V_DD = 15 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

Medium-speed operation - t_PHL = 90 ns; t_PLH = 140 ns (typ.) at 10 V
INHIBIT and ENABLE inputs
Buffered outputs
100% tested for quiescent current at 20 V
Maximum input leakage current of 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package temperature range):
    1 V at V_DD = 5 V
    2 V at V_DD = 10 V
    2.5 V at V_DD = 15 V
Standardized, symmetrical output characteristics
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of 'B' Series CMOS Devices"

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to V_SS and ENABLE/EXP to V_DD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4086B contains one 4-wide 2-input AND-OR-INVERT gate with an INHIBIT/(EXP\) input and an ENABLE/EXP input. For a 4-wide A-O-I function INHIBIT/(EXP\) is tied to V_SS and ENABLE/EXP to V_DD. See Fig. 10 and its associated explanation for applications where a capability greater than 4-wide is required.

The CD4086B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrink small-outline packages (PW and PWR suffixes).

filter

Buscar otro/a Compuertas combinadas

Descargar

Documentación técnica

No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.

Ver todo 1

Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	CD4086B TYPES datasheet (Rev. C)			21/08/2003

CD4086B-MIL

Puerta AND OR INVERT con CMOS expandible de doble entrada y ancho 4

CD4086B-MIL

Detalles del producto

Documentación técnica

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI