Inicio Interfaz Circuitos integrados de interfaz digital serie (SDI)

LMH0340

ACTIVO

Serializador HD/SD DVB-ASI 3G SDI y controlador con interfaz LVDS

Detalles del producto

Function Serializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 475 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
Function Serializer Supply voltage (V) 2.5, 3.3 Power consumption (mW) 475 Data rate (max) (Mbps) 2970 Control interface Pin/SMBus Operating temperature range (°C) -40 to 85
WQFN (RHS) 48 49 mm² 7 x 7
  • LVDS Interface to Host FPGA
  • No External VCO or Clock Ref Required
  • Integrated Variable Output Cable Driver
  • 3.3V SMBus Configuration Interface
  • Integrated TXCLK PLL Cleans Clock Noise
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to 85°C

Key Specifications

  • Output Compliant With SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
  • Typical Power Dissipation: 440 mW
  • 30 ps Typical Output Jitter (HD, 3G)

All trademarks are the property of their respective owners.

  • LVDS Interface to Host FPGA
  • No External VCO or Clock Ref Required
  • Integrated Variable Output Cable Driver
  • 3.3V SMBus Configuration Interface
  • Integrated TXCLK PLL Cleans Clock Noise
  • Small 48-Pin WQFN Package
  • Industrial Temperature range: -40°C to 85°C

Key Specifications

  • Output Compliant With SMPTE 424M, SMPTE 292M, SMPTE 259M-C and DVB-ASI
  • Typical Power Dissipation: 440 mW
  • 30 ps Typical Output Jitter (HD, 3G)

All trademarks are the property of their respective owners.

The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See for details on which Standards are supported per device.

The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver.

The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48-pin WQFN package.

The LMH0340/0040/0070/0050 SDI Serializers are part of TI’s family of FPGA-Attach SER/DES products supporting 5-bit LVDS interfaces with FPGAs. An FPGA Host will format data with supplied IP such that the output of the LMH0340 is compliant with the requirements of DVB-ASI, SMPTE 259M-C, SMPTE 292M and SMPTE 424M standards. See for details on which Standards are supported per device.

The interface between the SER (Serializer) and the FPGA consists of a 5 bit wide LVDS data bus, an LVDS clock and an SMBus interface. The LMH0340/0040/0070 SER devices include an integrated cable driver which is fully compliant with all of the SMPTE specifications listed above. The LMH0050 has a CML output driver that can drive a differential transmission line or interface to a cable driver.

The FPGA-Attach SER/DES family is supported by a suite of IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is packaged in a physically small 48-pin WQFN package.

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Documentación técnica

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Tipo Título Fecha
* Data sheet LMH0340/040/070/050 3Gbps, HD, SD, DVB-ASI SDI Serializr & Cable Drvr w/LVDS I/F datasheet (Rev. I) 16 abr 2013
Selection guide Broadcast and Professional Video Interface Solutions (Rev. E) 05 abr 2017
Application note AN-1943 Understanding Serial Digital Video Bit Rates (Rev. A) 26 abr 2013
Application note AN-1972 Board Layout Challenges in Serial Digital Interface (Rev. C) 26 abr 2013
Application note AN-1988 LMH0340 / LMH0341 SerDes Family LVDS Timing Overview (Rev. A) 26 abr 2013
Application note AN-2145 Power Considerations for SDI Products (Rev. B) 26 abr 2013
Application note AN-2146 Power Design for SDI and Other Noise-Sensitive Devices (Rev. A) 26 abr 2013
Application note Triple Rate SDI IP FPGA Resource Utilization on SDXILEVK/AES-EXP-SDI-G Ref Dsgn (Rev. A) 26 abr 2013
User guide SDALTEVK HSMC SDI Adapter board 05 mar 2012
User guide Triple-Rate SDI and Video Clocking Daughter Card 26 ene 2012
Application note High-Speed Board Layout Challenges in FPGA/SDI Sub-Systems 12 nov 2009
Application note DS25CP104 in 3G SDI Router Application 20 ago 2008
Application note A 3 Gbps SDI Connectivity Solution Supporting Uncompressed 1080p60 Video 18 mar 2008
Design guide Broadcast Video Owner's Manual 17 nov 2006

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Ejemplo de código o demostración

BROADCAST_VIDEO_SERDES_IP — Código de soporte de video de difusión para interfaz LVDS SDI SerDes

We have developed a family of serializers and deserializers intended to support the serial digital interface (SDI) standards of the Society of Motion Picture and Television Engineers (SMPTE). These devices connect to a host FPGA through a moderate speed, moderate width (600 Mbps, 5 bits wide) (...)
Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Herramienta de simulación

TINA-TI — Programa de simulación analógica basado en SPICE

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
Guía del usuario: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
WQFN (RHS) 48 Ultra Librarian

Pedidos y calidad

Información incluida:
  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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