SN74AUP1T157
- Single-Supply Voltage Translator
- Output Level Up to Supply VCC CMOS Level
- 1.8 V to 3.3 V (at VCC = 3.3 V)
- 2.5 V to 3.3 V (at VCC = 3.3 V)
- 1.8 V to 2.5 V (at VCC = 2.5 V)
- 3.3 V to 2.5 V (at VCC = 2.5 V
- Schmitt-Trigger Inputs Reject Input Noise and Provide
Better Output Signal Integrity - Ioff Supports Partial Power Down (VCC = 0 V)
- Very Low Static Power Consumption:
0.1 µA - Very Low Dynamic Power Consumption:
0.9 µA - Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- Pb-Free Packages Available: SC-70 (DCK)
2 x 2.1 x 0.65 mm (Height 1.1 mm) - More Gate Options Available at www.ti.com/littlelogic
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model
(A114-B, Class II) - 1000-V Charged-Device Model (C101)
- 2000-V Human-Body Model
The SN74AUP1T157 is a single 2-input multiplexer that selects data from two data inputs (A and B) under control of a common data select input (C). The state of the common data select input determines the particular register from which the data comes. The output (Y) presents the selected data in the true (non-inverted) form.
AUP technology is the industrys lowest-power logic technology designed for use in extending battery-life in operating. All input levels that accept 1.8-V LVCMOS signals, while operating from either a single 3.3-V or 2.5-V VCC supply. This product also maintains excellent signal integrity (see Figure 2 and Figure 3).
The wide VCC range of 2.3 V to 3.6 V allows the possibility of switching output level to connect to external controllers or processors.
Schmitt-trigger inputs (VT = 210 mV between positive and negative input transitions) offer improved noise immunity during switching transitions, which is especially useful on analog mixed-mode designs. Schmitt-trigger inputs reject input noise, ensure integrity of output signals, and allow for slow input signal transition.
Ioff is a feature that allows for powered-down conditions (VCC = 0 V) and is important in portable and mobile applications. When VCC = 0 V, signals in the range from 0 V to 3.6 V can be applied to the inputs and outputs of the device. No damage occurs to the device under these conditions.
The SN74AUP1T157 is designed with optimized current-drive capability of 4 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.
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技術資料
種類 | タイトル | 最新の英語版をダウンロード | 日付 | |||
---|---|---|---|---|---|---|
* | データシート | Low Power, 1.8/2.5/3.3-V In, 3.3-V CMOS Out, Buffer Multiplexer (Noninverted) データシート | 2010年 4月 16日 | |||
セレクション・ガイド | Voltage Translation Buying Guide (Rev. A) | 2021年 4月 15日 | ||||
アプリケーション概要 | Understanding Schmitt Triggers (Rev. A) | PDF | HTML | 2019年 5月 22日 |
設計および開発
その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。
5-8-LOGIC-EVM — 5 ~ 8 ピンの DCK、DCT、DCU、DRL、DBV の各パッケージをサポートする汎用ロジックの評価基板 (EVM)
パッケージ | ピン数 | CAD シンボル、フットプリント、および 3D モデル |
---|---|---|
SOT-SC70 (DCK) | 6 | Ultra Librarian |
購入と品質
- RoHS
- REACH
- デバイスのマーキング
- リード端子の仕上げ / ボールの原材料
- MSL 定格 / ピーク リフロー
- MTBF/FIT 推定値
- 使用原材料
- 認定試験結果
- 継続的な信頼性モニタ試験結果
- ファブの拠点
- 組み立てを実施した拠点