DS125DF1610
- Pin-Compatible Family
- DS150DF1610: 12.5 to 15 G
- DS125DF1610: 9.8 to 12.5 G
- DS110DF1610: 8.5 to 11.3 G
- 4x4 Analog Cross Point Switch for Each Quad
- Fully Adaptive CTLE
- Self tuning DFE, with Optional Continuous Adaption
- Configurable VGA
- Adjustable Transmit VOD
- Adjustable 3-tap Transmit FIR Filter
- On-chip AC Coupling on Receive Inputs
- Locks to Half/Quarter/Eighth Data Rates for Legacy Support
- On-chip Eye Monitor(EOM), PRBS Checker, Pattern Generator
- Supports JTAG Boundary Scan
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection
- Single 2.5 V ±5% Power Supply
- SMBus Based Register Configuration
- Optional EEPROM Configuration
- 15 mm × 15 mm, 196-pin FCBGA Package
- Operating Temp Range : –40°C to +85°C
The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.
Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.
Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 | |
|---|---|---|---|---|---|---|
| * | 데이터 시트 | DS125DF1610 9.8 to 12.5 Gbps 16-Channel Retimer datasheet (Rev. B) | PDF | HTML | 2017. 1. 13 | ||
| 애플리케이션 노트 | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023. 1. 31 | ||||
| 기술 문서 | Eye doctor: Reflections and how to deal with them in high-speed systems | PDF | HTML | 2016. 9. 8 | |||
| 아날로그 디자인 학술지 | Green box testing: A method for optimizing high-speed serial links | 2016. 7. 21 | ||||
| 애플리케이션 노트 | Understanding EEPROM Programming for 10G to 12.5G Retimers | PDF | HTML | 2016. 1. 13 | |||
| 애플리케이션 노트 | Selecting TI SigCon Devices for SFF-8431 SFP+ Applications | 2014. 5. 6 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS125DF1610EVM — 9.8~12.5.5Gbps 16채널 리타이머 평가 모듈
The DS125DF1610EVM allows for easy evaluation of the DS125DF1610. Users are required to supply power and high speed traffic to the EVM via the SMA connectors. A low cost on board oscillator provides a reference clock for the DS125DF1610’s PPM counter, so external clocking equipment is not (...)
TIDA-00426 — 12Gbps 멀티 채널 BERT 보드 레퍼런스 디자인
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| FCBGA (ABB) | 196 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.