DS125DF1610
- Pin-Compatible Family
- DS150DF1610: 12.5 to 15 G
- DS125DF1610: 9.8 to 12.5 G
- DS110DF1610: 8.5 to 11.3 G
- 4x4 Analog Cross Point Switch for Each Quad
- Fully Adaptive CTLE
- Self tuning DFE, with Optional Continuous Adaption
- Configurable VGA
- Adjustable Transmit VOD
- Adjustable 3-tap Transmit FIR Filter
- On-chip AC Coupling on Receive Inputs
- Locks to Half/Quarter/Eighth Data Rates for Legacy Support
- On-chip Eye Monitor(EOM), PRBS Checker, Pattern Generator
- Supports JTAG Boundary Scan
- Programmable Output Polarity Inversion
- Input Signal Detection, CDR Lock Detection
- Single 2.5 V ±5% Power Supply
- SMBus Based Register Configuration
- Optional EEPROM Configuration
- 15 mm × 15 mm, 196-pin FCBGA Package
- Operating Temp Range : –40°C to +85°C
The DS125DF1610 is a sixteen-channel multi-rate retimer with integrated signal conditioning features. The device includes a fully adaptive Continuous Time Linear Equalizer (CTLE), Decision Feedback Equalizer (DFE), clock and data recovery (CDR), and a transmit FIR filter to enhance the reach and robustness over long, lossy, crosstalk impaired high speed serial links to achieve BER < 1×10-15.
Each channel of the DS125DF1610 independently locks to serial data at 9.8 to 12.5 Gbps and the divide by 2, 4 and 8 sub-multiples. A simple external oscillator (±100ppm) that is synchronous or asynchronous with the incoming data stream is used as a reference clock. Integrated 4x4 cross point switches allow for full non-blocking routing or broadcasting within each quad of the DS125DF1610.
Programmable transmit FIR filter offers control of the pre-cursor, main tap and post-cursor for transmit equalization. The fully adaptive receive equalization (CTLE and DFE) enables longer distance transmission in lossy copper interconnects and backplanes with multiple connectors.
A non-disruptive mission mode eye-monitor feature allows link monitoring internal to the receiver. The built-in PRBS generator and checker compliment the internal diagnostic features to complete standalone BERT measurements. Built-in JTAG enables manufacturing tests.
기술 자료
| 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DS125DF1610 9.8 to 12.5 Gbps 16-Channel Retimer datasheet (Rev. B) | PDF | HTML | 2017/01/13 |
| Application note | Extend reach with Ethernet Redrivers and Retimers for 10G-12.5G Applications (Rev. A) | 2023/01/31 | ||
| EVM User's guide | DS125DF1610EVM User's Guide (Rev. B) | 2018/09/20 | ||
| Technical article | Eye doctor: Reflections and how to deal with them in high-speed systems | PDF | HTML | 2016/09/08 | |
| Analog Design Journal | Green box testing: A method for optimizing high-speed serial links | 2016/07/21 | ||
| Application note | Understanding EEPROM Programming for 10G to 12.5G Retimers | 2016/01/13 | ||
| Application note | Selecting TI SigCon Devices for SFF-8431 SFP+ Applications | 2014/05/06 |
설계 및 개발
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DS125DF1610EVM — 9.8~12.5.5Gbps 16채널 리타이머 평가 모듈
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TIDA-00426 — 12Gbps 멀티 채널 BERT 보드 레퍼런스 디자인
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| FCBGA (ABB) | 196 | Ultra Librarian |
주문 및 품질
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
- 팹 위치
- 조립 위치
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.