SN74AVC2T244

활성

듀얼 비트 듀얼 공급 버스 트랜시버

제품 상세 정보

Technology family AVC Bits (#) 2 Configuration 2 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.81 High input voltage (max) (V) 3.6 Vout (min) (V) 3000 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -24 IOL (max) (mA) -24 Supply current (max) (µA) 3.6 Features 1.4, 2.16 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 85
Technology family AVC Bits (#) 2 Configuration 2 Ch A to B 0 Ch B to A High input voltage (min) (V) 0.81 High input voltage (max) (V) 3.6 Vout (min) (V) 3000 Vout (max) (V) 3.6 Data rate (max) (Mbps) 380 IOH (max) (mA) -24 IOL (max) (mA) -24 Supply current (max) (µA) 3.6 Features 1.4, 2.16 Input type Standard CMOS Output type 3-State, Balanced CMOS Rating Catalog Operating temperature range (°C) -40 to 85
X2SON (DQE) 8 1.4 mm² 1.4 x 1 X2SON (DQM) 8 2.16 mm² 1.8 x 1.2
  • Wide Operating VCC Range of 0.9 V to 3.6 V
  • Low Static-Power Consumption, 6-µA Max ICC
  • Output Enable Feature Allows User to Disable Outputs to Reduce Power Consumption
  • ±24-mA Output Drive at 3.0 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Maximum Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000-V Human-Body Model (A114-A)
  • Wide Operating VCC Range of 0.9 V to 3.6 V
  • Low Static-Power Consumption, 6-µA Max ICC
  • Output Enable Feature Allows User to Disable Outputs to Reduce Power Consumption
  • ±24-mA Output Drive at 3.0 V
  • Ioff Supports Partial Power-Down-Mode Operation
  • Input Hysteresis Allows Slow Input Transition and Better Switching Noise Immunity at Input
  • Maximum Data Rates
    • 380 Mbps (1.8-V to 3.3-V Translation)
    • 200 Mbps (<1.8-V to 3.3-V Translation)
    • 200 Mbps (Translate to 2.5 V or 1.8 V)
    • 150 Mbps (Translate to 1.5 V)
    • 100 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000-V Human-Body Model (A114-A)

This 2-bit unidirectional translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 0.9 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 0.9 V to 3.6 V. This allows for low-voltage translation between 0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.6-V voltage nodes. For the SN74AVC2T244, when the output-enable ( OE) input is high, all outputs are placed in the high-impedance state. The SN74AVC2T244 is designed so that the OE input circuit is referenced to VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This 2-bit unidirectional translator uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 0.9 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 0.9 V to 3.6 V. This allows for low-voltage translation between 0.9-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V and 3.6-V voltage nodes. For the SN74AVC2T244, when the output-enable ( OE) input is high, all outputs are placed in the high-impedance state. The SN74AVC2T244 is designed so that the OE input circuit is referenced to VCCA. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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기술 문서

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모두 보기15
유형 직함 날짜
* Data sheet SN74AVC2T244 2-Bit Unidirectional Voltage-level Translator datasheet (Rev. C) PDF | HTML 2021/03/12
Selection guide Voltage Translation Buying Guide (Rev. A) 2021/04/15
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 2015/04/30
EVM User's guide SN74AVC2T244EVM 2011/09/19
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
More literature LCD Module Interface Application Clip 2003/05/09
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 2002/08/20
More literature Standard Linear & Logic for PCs, Servers & Motherboards 2002/06/13
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002/05/22
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 1999/07/07
Application note AVC Logic Family Technology and Applications (Rev. A) 1998/08/26

설계 및 개발

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평가 보드

SN74AVC2T244EVM — SN74AVC2T244 평가 모듈

The SN74AVC2T244 is a 2-bit voltage level translator. This translator is a single direction voltage translator, with OE. When the output-enable (OE) input is high, all outputs are placed in the high-impedance state. The A port is designed to track VCCA. VCCA accepts any supply voltage from 0.9V to (...)

사용 설명서: PDF
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평가 보드

TAS6424EQ1EVM — 75W, 2MHz, 쿼드 채널 디지털 입력 클래스 D 오디오 증폭기 TAS6424E-Q1 평가 모듈

TAS6424EQ1EVM 평가 모듈(EVM)은 오토모티브 인포테인먼트용 TAS6424E-Q1, 2.1MHz, 4채널, 디지털 입력 클래스 D 오디오 증폭기 솔루션을 보여줍니다. 2.1MHz 스위칭 주파수를 사용하면 인덕터 크기를 크게 줄일 수 있습니다. TAS6424E-Q1은 채널당 25W(10% THD+N)을 4Ω로 제공하며 14.4V 공급으로 I2C 진단 및 보호 기능을 통합합니다. TAS6424E-Q1에는 CISPR25 Class 5 EMI 규정 준수 표준을 충족하는 확산 스펙트럼 기술이 포함되어 있습니다.
사용 설명서: PDF | HTML
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시뮬레이션 모델

SN74AVC2T244 IBIS Model

SCEM543.ZIP (55 KB) - IBIS Model
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패키지 다운로드
X2SON (DQE) 8 옵션 보기
X2SON (DQM) 8 옵션 보기

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

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