DS80EP100
- 5 to 12.5 Gbps Operation
- No Power or Ground Required
- Equalization Effective Anywhere in Data Path
- Equalizes CML, LV-PECL, LVDS Signals
- Symmetric I/O Structures Provide Equal Boost for Bi-directional Operation
- 7 dB Maximum Boost
- Code Independent, 8b/10b or Scrambled
- Supports Both Bi-level and Multi-level Signaling
- Extends Reach Over Backplanes and Cables
- Compatible with PCI-Express Gen1 and Gen2
- Compatible with XAUI
- Will Operate in Series with Existing Active Equalizer
- Easy to Handle 6 Pin WSON
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TI’s Power-saver equalizer compensates for transmission medium losses and minimizes medium-induced deterministic jitter. Performance is guaranteed over the full range of 5 to 12.5 Gbps. The DS80EP100 requires no power to operate. The equalizer operates anywhere in the data path to minimize media-induced deterministic jitter in both FR4 traces and cable applications. Symmetric I/O structures support full duplex or half duplex applications. Linear compensation is provided independent of line coding or protocol. The device is ideal for both bi-level and multi-level signaling.
The equalizer is available in a 6 pin leadless WSON package with a space saving 2.2 mm X 2.5 mm footprint. This tiny package provides maximum flexibility in placement and routing of the Power-saver equalizer.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DS80EP100 5 to 12.5 Gbps, Power-Saver Equalizer for Backplanes and Cables datasheet (Rev. C) | 2013年 2月 19日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
WSON (NGF) | 6 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。