DS90LV004
- 1.5 Gbps data rate per channel
- Configurable pre-emphasis drives lossy backplanes and cables
- Low output skew and jitter
- LVDS/CML/LVPECL compatible input, LVDS output
- On-chip 100Ω input and output termination
- 12 kV ESD protection on LVDS outputs
- Single 3.3V supply
- Very low power consumption
- Industrial -40 to +85°C temperature range
- Small TQFP Package Footprint
- Evaluation Kit Available
- See SCAN90004 for JTAG-enabled version
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The DS90LV004 is a four channel 1.5 Gbps LVDS buffer/repeater. High speed data paths and flow-through pinout minimize internal device jitter and simplify board layout, while configurable pre-emphasis overcomes ISI jitter effects from lossy backplanes and cables. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18- bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs and outputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. The repeater function is especially useful for boosting signals for longer distance transmission over lossy cables and backplanes.
技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | DS90LV004 4-Channel LVDS Buffer/Repeater with Pre-Emphasis datasheet (Rev. P) | 2013年 4月 17日 | |
Application note | Signaling Rate vs. Distance for Differential Buffers | 2010年 1月 26日 | ||
White paper | Overcoming Impedance Discontins in HS Signal Paths Using LVDS Sgnl Cnditionrs | 2006年 5月 1日 | ||
Application note | LVDS Signal Quality: Jitter Measurements Using Eye Patterns Test Report #1 | 1998年 10月 5日 |
設計與開發
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PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
TQFP (PFB) | 48 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。