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產品詳細資料

Number of channels 2 Output type Push-Pull Propagation delay time (µs) 4 Vs (max) (V) 15 Vs (min) (V) 2.7 Vos (offset voltage at 25°C) (max) (mV) 5 Iq per channel (typ) (mA) 0.006 Input bias current (±) (max) (nA) 0.0004 Rail-to-rail In Rating Catalog Operating temperature range (°C) -40 to 85 VICR (max) (V) 15.2 VICR (min) (V) -0.2
Number of channels 2 Output type Push-Pull Propagation delay time (µs) 4 Vs (max) (V) 15 Vs (min) (V) 2.7 Vos (offset voltage at 25°C) (max) (mV) 5 Iq per channel (typ) (mA) 0.006 Input bias current (±) (max) (nA) 0.0004 Rail-to-rail In Rating Catalog Operating temperature range (°C) -40 to 85 VICR (max) (V) 15.2 VICR (min) (V) -0.2
SOIC (D) 8 29.4 mm² 4.9 x 6
  • (Typical Unless Otherwise Noted)
  • Low Power Consumption (Max): IS = 10 μA/comp
  • Wide Range of Supply Voltages: 2.7V to 15V
  • Rail-To-Rail Input Common Mode Voltage Range
  • Rail-To-Rail Output Swing (Within 100 mV of the Supplies, @ V+ = 2.7V, and ILOAD = 2.5 mA)
  • Short Circuit Protection: 40 mA
  • Propagation Delay (@ V+ = 5V, 100 mV Overdrive): 4 μs

All trademarks are the property of their respective owners.

  • (Typical Unless Otherwise Noted)
  • Low Power Consumption (Max): IS = 10 μA/comp
  • Wide Range of Supply Voltages: 2.7V to 15V
  • Rail-To-Rail Input Common Mode Voltage Range
  • Rail-To-Rail Output Swing (Within 100 mV of the Supplies, @ V+ = 2.7V, and ILOAD = 2.5 mA)
  • Short Circuit Protection: 40 mA
  • Propagation Delay (@ V+ = 5V, 100 mV Overdrive): 4 μs

All trademarks are the property of their respective owners.

The LMC6762 is an ultra low power dual comparator with a maximum supply current of 10 μA/comparator. It is designed to operate over a wide range of supply voltages, from 2.7V to 15V. The LMC6762 has ensured specifications at 2.7V to meet the demands of 3V digital systems.

The LMC6762 has an input common-mode voltage range which exceeds both supplies. This is a significant advantage in low-voltage applications. The LMC6762 also features a push-pull output that allows direct connections to logic devices without a pull-up resistor.

A quiescent power consumption of 50 μW/amplifier (@ V+ = 5V) makes the LMC6762 ideal for applications in portable phones and hand-held electronics. The ultra-low supply current is also independent of power supply voltage. Ensured operation at 2.7V and a rail-to-rail performance makes this device ideal for battery-powered applications.

Refer to the LMC6772 datasheet for an open-drain version of this device.

The LMC6762 is an ultra low power dual comparator with a maximum supply current of 10 μA/comparator. It is designed to operate over a wide range of supply voltages, from 2.7V to 15V. The LMC6762 has ensured specifications at 2.7V to meet the demands of 3V digital systems.

The LMC6762 has an input common-mode voltage range which exceeds both supplies. This is a significant advantage in low-voltage applications. The LMC6762 also features a push-pull output that allows direct connections to logic devices without a pull-up resistor.

A quiescent power consumption of 50 μW/amplifier (@ V+ = 5V) makes the LMC6762 ideal for applications in portable phones and hand-held electronics. The ultra-low supply current is also independent of power supply voltage. Ensured operation at 2.7V and a rail-to-rail performance makes this device ideal for battery-powered applications.

Refer to the LMC6772 datasheet for an open-drain version of this device.

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類型 標題 日期
* Data sheet LMC6762 Dual MicroPower Rail-To-Rail Input CMOS Comparator with Push-Pull Output datasheet (Rev. D) 2013年 3月 26日
E-book The Signal e-book: A compendium of blog posts on op amp design topics 2017年 3月 28日
More literature Die D/S LMC6762 MDA Dual Micro-Pwr Rail-Rail Input Cmos Compw/ Push-Pull Output 2012年 9月 28日

設計與開發

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模擬型號

LMC6762 PSPICE Model

SNOM174.ZIP (4 KB) - PSpice Model
模擬工具

PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
模擬工具

TINA-TI — 基於 SPICE 的類比模擬程式

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
使用指南: PDF
參考設計

TIDA-01022 — 適用於 DSO、雷達和 5G 無線測試系統的靈活 3.2-GSPS 多通道 AFE 參考設計

This high speed multi-channel data capture reference design enables optimum system performance. System designers needs to consider critical design parameters like clock jitter and skew for high speed multi-channel clock generation, which affects overall system SNR, SFDR, channel to channel skew (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01027 — 在 12.8 GSPS 資料採集系統中發揮最大效能的低雜訊電源供應參考設計

This reference design demonstrates an efficient, low-noise five-rail power supply design for very high-speed Data Acquisition (DAQ) systems capable of > 12.8 GSPS. The power supply DC/DC converters are frequency-synchronized and phase-shifted in order to minimize input current ripple and (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01028 — 適用於高速示波器和寬頻帶數位器的 12.8-GSPS 類比前端參考設計

This reference design provides a practical example of interleaved RF-sampling analog-to-digital converters (ADCs) to achieve a 12.8-GSPS sampling rate. This is done by time interleaving two RF-sampling ADCs. Interleaving requires a phase shift between the ADCs, which this reference design achieves (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010128 — 適用於 12 位元數位器的可擴充 20.8 GSPS 參考設計

This reference design describes a 20.8 GSPS sampling system using RF sampling analog-to-digital converters (ADCs) in time interleaved configuration. Time interleaving method is a proven and traditional way of increasing sample rate, however, matching individual ADCs offset, gain and sampling time (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-010122 — 適用於多通道射頻系統的參考設計同步數據轉換器 DDC 和 NCO 功能

此參考設計可解決與新興 5G 適配應用相關,例如大規模多輸入多輸出 (mMIMO)、相位陣列雷達與通訊酬載等應用相關的同步設計挑戰。一般 RF 前端包含天線、低雜訊放大器 (LNA)、混波器、類比網域中的本地振盪器 (LO) 及類比轉數位轉換器、數值控制振盪器 (NCO) 和數位降轉換器 (DDC)。為了達到整體系統同步化,這些數位區塊必須與系統時鐘同步。本參考設計採用 ADC12DJ3200 資料轉換器,透過同步處理晶片內建 NCO 與 SYNC ~ 並使用無雜訊孔徑延遲調整 (tAD 調整) 功能,在多個接收器之間達到小於 5-ps 的頻道間偏斜的效果,以進一步降低偏斜。此設計也具備搭載 (...)
Design guide: PDF
電路圖: PDF
參考設計

TIDA-01442 — 適用於 L、S、C 和 X 波段的直接射頻取樣雷達接收器參考設計

此參考設計利用 ADC12DJ3200 評估模組 (EVM),展示用於以 HF、VHF、UHF、L、S、C 和 X 波段的一部分操作雷達的直接射頻取樣接收器。類比轉數位轉換器 (ADC) 的廣泛類比輸入頻寬與高取樣率 (6.4 GSPS),採用單或雙 ADC 提供多頻段範圍。ADC 的直接射頻取樣功能,可透過省去數個向下轉換階段減少零組件數量,進而降低整體系統複雜性。
Design guide: PDF
電路圖: PDF
參考設計

TIDA-00431 — 採用 8 GHz DC 耦合差動放大器的射頻取樣 4 GSPS ADC 參考設計

Wideband radio frequency (RF) receivers allow greatly increased flexibility in radio designs. The wide instantaneous bandwidth allows flexible tuning without changing hardware and the ability to capture multiple channels at widely separated frequencies.

This reference design describes a wideband RF (...)

Design guide: PDF
電路圖: PDF
參考設計

TIDA-00826 — 50 Ohm 2 GHz 示波器前端參考設計

This reference design is part of an analog front-end for 50Ω-input oscilloscope application. System designers can readily use this evaluation platform to process input signals from DC to 2 GHz in both frequency-domain and time-domain applications.
Design guide: PDF
電路圖: PDF
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