SCANSTA112
- True IEEE 1149.1 Hierarchical and Multidrop Addressable Capability
- The 8 Address Inputs Support up to 249 Unique Slot Addresses, an Interrogation Address, Broadcast Address, and 4 Multi-Cast Group Addresses (Address 000000 is Reserved)
- 7 IEEE 1149.1-Compatible Configurable Local Scan Ports
- Bi-directional Backplane and LSP0 Ports are Interchangeable Slave Ports
- Capable of Ignoring TRST of the Backplane Port when it Becomes the Slave.
- Stitcher Mode Bypasses Level 1 and 2 Protocols
- Mode Register0 Allows Local TAPs to be Bypassed, Selected for Insertion into the Scan Chain Individually, or Serially in Groups of Two or Three
- Transparent Mode can be Enabled with a Single Instruction to Conveniently Buffer the Backplane IEEE 1149.1 Pins to Those on a Single Local Scan Port
- General Purpose Local Port Pass Through Bits are Useful for Delivering Write Pulses for Flash Programming or Monitoring Device Status.
- Known Power-Up State
- TRST on all Local Scan Ports
- 32-bit TCK Counter
- 16-bit LFSR Signature Compactor
- Local TAPs can Become TRI-STATE via the OE Input to Allow an Alternate Test Master to Take Control of the Local TAPs (LSP0-3 have a TRI-STATE Notification Output)
- 3.0-3.6V VCC Supply Operation
- Supports Live Insertion/Withdrawal
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The SCANSTA112 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA112 supports up to 7 local IEEE1149.1 scan chains which can be accessed individually or combined serially.
Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.
The STA112 has a unique feature in that the backplane port and the LSP0 port are bidirectional. They can be configured to alternatively act as the master or slave port so an alternate test master can take control of the entire scan chain network from the LSP0 port while the backplane port becomes a slave.
技術文件
| 重要文件 | 類型 | 標題 | 格式選項 | 下載最新的英文版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 資料表 | SCANSTA112 7-Port Multidrop IEEE 1149.1 (JTAG) Multiplexer datasheet (Rev. I) | 2013/4/12 | |||
| 應用說明 | Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D) | 2013/4/26 | ||||
| 應用說明 | AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B) | 2013/4/26 | ||||
| 應用說明 | AN-1259 SCANSTA112 Designer's Reference (Rev. H) | 2013/4/26 | ||||
| 應用說明 | Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C) | 2013/4/26 | ||||
| 更多文件說明 | SCANSTA112 7-port Multidrop IEEE 1149.1 (JTAG) Multiplexer Evaluation Kit Docume | 2012/2/21 | ||||
| 應用說明 | SCANSTA112 Quick Reference Guide | 2010/1/7 | ||||
| 應用說明 | JTAG Advanced Capabilities and System Design | 2009/3/19 | ||||
| 應用說明 | Partition IEEE 1149.1 SCAN Chains for Manageability! | 2003/3/6 |
設計與開發
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EVF-WORKBENCH-CONVERTER-SW — EVF Workbench - Converts JTAG SVF to National’s EVF2 SCAN Format
| 封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
|---|---|---|
| QFP (NEZ) | 100 | Ultra Librarian |
| NFBGA (NZD) | 100 | Ultra Librarian |
訂購與品質
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