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The SCANSTA111 extends the IEEE Std. 1149.1 test bus into a multidrop test bus environment. The advantage of a multidrop approach over a single serial scan chain is improved test throughput and the ability to remove a board from the system and retain test access to the remaining modules. Each SCANSTA111 supports up to 3 local IEEE 1149.1 scan rings which can be accessed individually or combined serially. Addressing is accomplished by loading the instruction register with a value matching that of the Slot inputs. Backplane and inter-board testing can easily be accomplished by parking the local TAP Controllers in one of the stable TAP Controller states via a Park instruction. The 32-bit TCK counter enables built in self test operations to be performed on one port while other scan chains are simultaneously tested.
| 類型 | 標題 | 日期 | ||
|---|---|---|---|---|
| * | Data sheet | SCANSTA111 Enhanced SCAN Bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port datasheet (Rev. K) | 2013年 4月 12日 | |
| Application note | AN-1259 SCANSTA112 Designer's Reference (Rev. H) | 2013年 4月 26日 | ||
| Application note | AN-1312 SCANSTA111/SCANSTA112 Scan Bridge Timing (Rev. B) | 2013年 4月 26日 | ||
| Application note | Simplified Program of Xilinx Devices Using a SCANSTA111/112 JTAG Scan Chain Mux (Rev. C) | 2013年 4月 26日 | ||
| Application note | Simplified Programming of Altera FPGAs Using CSANSTA111/112 JTAG Scan Chain Mux (Rev. D) | 2013年 4月 26日 | ||
| Application note | JTAG Advanced Capabilities and System Design | 2009年 3月 19日 | ||
| Application note | Partition IEEE 1149.1 SCAN Chains for Manageability! | 2003年 3月 6日 |
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