SN65HVD10
- Operates with a 3.3-V supply
- Bus-pin ESD protection exceeds 16-kV HBM
- 1/8 Unit-load option available (up to 256 nodes on the bus)
- Optional driver output transition times for signaling rates (1)of 1 Mbps, 10 Mbps, and 32 Mbps
- Meets or exceeds the requirements of ANSI TIA/EIA-485-A
- Bus-pin short-circuit protection from –7 V to 12 V
- Low-current standby mode: 1 µA, typical
- Open-circuit, idle-bus, and shorted-bus fail-safe receiver
- Thermal shutdown protection
- Glitch-free power-up and power-down protection for hot-plugging applications
- SN75176 footprint
(1)The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
The SN65HVD10, SN75HVD10, SN65HVD11, SN75HVD11, SN65HVD12, and SN75HVD12 bus transceivers all combine a 3-state differential line driver, as well as a differential input line receiver that operates with a single 3.3-V power supply. They are designed for balanced transmission lines and meet or exceed ANSI standard TIA/EIA-485-A and ISO 8482:1993. These differential bus transceivers are monolithic integrated circuits, designed for bidirectional data communication on multipoint bus-transmission lines. The drivers and receivers have active-high and active-low enables, that can be externally connected together to function as direction control. Very low device standby supply current, can be achieved by disabling the driver and the receiver.
The driver differential outputs and receiver differential inputs connect internally to form a differential input/output (I/O) bus port, that is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. These parts feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.
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技術文件
類型 | 標題 | 日期 | ||
---|---|---|---|---|
* | Data sheet | SNx5HVD1x 3.3-V RS-485 Transceivers datasheet (Rev. P) | PDF | HTML | 2022年 2月 16日 |
EVM User's guide | RS-485 Half-Duplex EVM User's Guide (Rev. C) | PDF | HTML | 2021年 9月 1日 | |
Application note | Operating RS-485 transceivers at fast signaling rates (Rev. A) | 2019年 2月 6日 | ||
Application note | The RS-485 Unit Load and Maximum Number of Bus Connections | 2004年 3月 15日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
RS485-HF-DPLX-EVM — RS-485 半雙工評估模組
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
TINA-TI — 基於 SPICE 的類比模擬程式
封裝 | 針腳 | CAD 符號、佔位空間與 3D 模型 |
---|---|---|
PDIP (P) | 8 | Ultra Librarian |
SOIC (D) | 8 | Ultra Librarian |
訂購與品質
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 認證摘要
- 進行中持續性的可靠性監測
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。