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SN74AUP2G08

現行

2 通道、2 輸入、0.8V 至 3.6V 低功耗 (< 1uA) AND 閘

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產品規格表

SN74AUP2G08

現行
產品規格表 立即訂購

產品詳細資料

Technology family AUP Number of channels 2 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family AUP Number of channels 2 Inputs per channel 2 IOL (max) (mA) 4 IOH (max) (mA) -4 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm) DSBGA (YFP) 8 1.8 mm² (— mm × — mm) X2SON (DQE) 8 1.4 mm² (1.4 mm × 1 mm) UQFN (RSE) 8 2.25 mm² (1.5 mm × 1.5 mm)
  • Wide operating VCC range of 0.8V to 3.6V
  • Low static-power consumption (ICC = 0.9µA max)
  • Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
  • 3.6V I/O tolerant to support mixed-mode signal operation
  • tpd = 5.9ns max at 3.3V
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • Wide operating VCC range of 0.8V to 3.6V
  • Low static-power consumption (ICC = 0.9µA max)
  • Low dynamic-power consumption (Cpd = 4.3pF typ at 3.3V)
  • Low noise – overshoot and undershoot <10% of VCC
  • Ioff supports partial-power-down mode operation
  • Schmitt-trigger action allows slow input transition and better switching noise immunity at the input (Vhys = 250mV Typ at 3.3V)
  • 3.6V I/O tolerant to support mixed-mode signal operation
  • tpd = 5.9ns max at 3.3V
  • Latch-up performance exceeds 100mA per JESD 78, Class II

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.

This dual 2-input positive-AND gate is designed for 0.8V to 3.6V VCC operation and performs the Boolean function Y = A ● B in positive logic.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when VCC = 0V, preventing damaging current backflow through the device when it is powered down.
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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74AUP2G08 Low-Power Dual 2-Input Positive-AND Gate datasheet (Rev. F) PDF | HTML 2025/5/18
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML 2025/4/17

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SN74AUP2G08 Behavioral SPICE Model

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VSSOP (DCU) 8 Ultra Librarian
DSBGA (YZP) 8 Ultra Librarian
DSBGA (YFP) 8 Ultra Librarian
X2SON (DQE) 8 Ultra Librarian
UQFN (RSE) 8 Ultra Librarian
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