計算工具
UCC21222
- Resistor-programmable dead time
- Universal: dual low-side, dual high-side or half-bridge driver
- 4A peak source, 6A peak sink output
- 3V to 5.5V input VCCI range
- Up to 18V VDD output drive supply
- 8V VDD UVLO
- Switching parameters:
- 28ns typical propagation delay
- 10ns minimum pulse width
- 5ns maximum delay matching
- 5.5ns maximum pulse-width distortion
- TTL and CMOS compatible inputs
- Integrated deglitch filter
- I/Os withstand –2V for 200ns
- Common-mode transient immunity (CMTI) greater than 100V/ns
- Isolation barrier life >40 Years
- Surge immunity up to 7800VPK
- Narrow body SOIC-16 (D) package
- Safety-related certifications (planned):
- 4242VPK isolation per DIN V VDE V 0884-11:2017-01 and DIN EN 61010-1
- 3000VRMS isolation for 1 minute per UL 1577
- CSA certification per IEC 60950-1, IEC 62368-1 and IEC 61010-1 end equipment standards
- CQC Certification per GB4943.1-2011
- Create a Custom Design Using the UCC21222 With the WEBENCH® Power Designer
The UCC21222 device is an isolated dual channel gate driver with programmable dead time. It is designed with 4A peak-source and 6A peak-sink current to drive power MOSFET, IGBT, and GaN transistors.
The device can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. A 5ns delay matching performance allows two outputs to be paralleled, doubling the drive strength for heavy load conditions without risk of internal shoot-through.
The input side is isolated from the two output drivers by a 3.0kVRMS isolation barrier, with a minimum of 100V/ns common-mode transient immunity (CMTI).
Resistor programmable dead time gives the capability to adjust dead time for system constraints to improve efficiency and prevent output overlap. Other protection features include a disable feature to shut down both outputs simultaneously when DIS is set high, an integrated deglitch filter that rejects input transients shorter than 5ns, and negative voltage handling for up to –2V spikes for 200ns on input and output pins. All supplies have UVLO protection.
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開發板
UCC21220EVM-009 — UCC21220 4A、6A 3.0kVRMS 隔離式雙通道閘極驅動器評估模組
UCC21220EVM-009 is designed for evaluating UCC21220, which is a 3.0-kVRMS Isolated Dual-Channel Gate Driver with 4.0-A source and 6.0-A sink peak current capability. This EVM could be served to evaluate the driver IC against its datsheet. The EVM can also be used as Driver IC component selection (...)
使用指南: PDF
模擬工具
PSPICE-FOR-TI — PSpice® for TI 設計與模擬工具
PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
參考設計
PMP41006 — 由 C2000™ 和 GaN 實現且具 CCM 圖騰柱 PFC 和電流模式 LLC 的 1-kW 參考設計
此參考設計將展示混合磁滯控制 (HHC) 方法，這是一種採用 C2000™ F28004x 微控制器之半橋 LLC 階段上的電流模式控制方式。硬體採用 TIDA-010062，這是 1-kW、80-Plus 鈦金屬、GaN CCM 圖騰柱免橋接 PFC 與半橋式 LLC 參考設計。針對混合磁滯控制新增獨立的感應卡，可在共振電容器上重新產生電壓。相較於單迴路電壓模式控制方法 (VMC)、HHC LLC 階段顯示較佳的暫態回應與簡單控制迴路設計。
Test report: PDF
參考設計
TIDA-010203 — 具 C2000 和 GaN 的 4-kW 單相圖騰柱 PFC 參考設計
This reference design is a 4-kW CCM totem-pole PFC with F280049/F280025 control card and LMG342x EVM board. This design demos a robust PFC solution, which avoids isolated current sense by putting the controller's ground in the middle of a MOSFET leg. Benefitting from non-isolation, AC current (...)
參考設計
PMP41043 — 由 C2000 和 GaN 實現且具 CCM 圖騰柱 PFC 和電流模式 LLC 的 1.6-kW 參考設計
此參考設計將展示混合磁滯控制 (HHC) 方法，是配備 C2000 F28004x 微控制器的半橋 LLC 階段上之電流模式控制方式。硬體以 TIDA-010062 為基礎，為 1-kW、80 Plus 鈦金屬、GaN CCM 圖騰柱免橋接 PFC 與半橋式 LLC 參考設計。針對混合磁滯控制新增獨立感應卡，可在共振電容器上重新產生電壓。
相較於單迴路電壓模式控制 (VMC) 方法，HHC LLC 階段展示較佳的暫態回應與簡單控制迴路設計。
Test report: PDF
| 封裝 | 引腳 | 下載 |
|---|---|---|
| SOIC (D) | 16 | 檢視選項 |
訂購與品質
內含資訊：
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊：
- 晶圓廠位置
- 組裝地點
建議產品可能具有與此 TI 產品相關的參數、評估模組或參考設計。