Product details

Sample rate (Max) (MSPS) 1000 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 69.7 ENOB (Bits) 11.3 SFDR (dB) 89 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 1000 Resolution (Bits) 14 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 69.7 ENOB (Bits) 11.3 SFDR (dB) 89 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 14-bit resolution, dual-channel, 1-GSPS ADC
  • Noise floor: –158 dBFS/Hz
  • Spectral performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 69.0 dBFS
    • NSD: –155.9 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and interleaving tones)
  • Spectral performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 66.3 dBFS
    • NSD: –153.3 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (except HD2, HD3, and interleaving tones)
  • Channel isolation: 100 dBc at fIN = 170 MHz
  • Input full-scale: 1.9 VPP
  • Input bandwidth (3 dB): 1.2 GHz
  • On-chip dither
  • Integrated wideband DDC block
  • JESD204B interface with subclass 1 support:
    • 2 lanes per ADC at 10.0 Gbps
    • 4 lanes per ADC at 5.0 Gbps
    • Support for multi-chip synchronization
  • Power dissipation: 1.35 W/ch at 1 GSPS
  • Package: 72-pin VQFNP (10 mm × 10 mm)
  • 14-bit resolution, dual-channel, 1-GSPS ADC
  • Noise floor: –158 dBFS/Hz
  • Spectral performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 69.0 dBFS
    • NSD: –155.9 dBFS/Hz
    • SFDR: 86 dBc (Including Interleaving Tones)
    • SFDR: 89 dBc (Except HD2, HD3, and interleaving tones)
  • Spectral performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 66.3 dBFS
    • NSD: –153.3 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (except HD2, HD3, and interleaving tones)
  • Channel isolation: 100 dBc at fIN = 170 MHz
  • Input full-scale: 1.9 VPP
  • Input bandwidth (3 dB): 1.2 GHz
  • On-chip dither
  • Integrated wideband DDC block
  • JESD204B interface with subclass 1 support:
    • 2 lanes per ADC at 10.0 Gbps
    • 4 lanes per ADC at 5.0 Gbps
    • Support for multi-chip synchronization
  • Power dissipation: 1.35 W/ch at 1 GSPS
  • Package: 72-pin VQFNP (10 mm × 10 mm)

The ADS54J40 is a low-power, wide-bandwidth, 14-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –158 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J40 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

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The ADS54J40 is a low-power, wide-bandwidth, 14-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –158 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10.0 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range and minimizes sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J40 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 14-bit data from each channel.

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Technical documentation

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* Data sheet ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter datasheet (Rev. C) 09 Jan 2018
EVM User's guide ADS54J40EVM User's Guide (Rev. A) 12 Jan 2016

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS54J40EVM — ADS54J40 Dual-Channel, 14-Bit, 1.0-GSPS Analog-to-Digital Converter Evaluation Module

The ADS54J40EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J40 and LMK04828 clock jitter cleaner. The ADS54J40 is a low power, 14-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. (...)

User guide: PDF
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Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards, (...)
Simulation model

ADS54J20/40/60 IBIS MODEL

SBAM205.ZIP (46 KB) - IBIS Model
Simulation model

ADS54J20/40/60 IBIS-AMI Model

SBAM325.ZIP (5519 KB) - IBIS-AMI Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-01378 — Wideband Receiver Reference Design for Upstream DOCSIS 3.1 Applications

This reference design consists of an analog front-end (AFE) signal chain for wideband receiver applications using the LMH2832 digitally controlled variable gain amplifier (DVGA) and ADS54J40 analog-to-digital converter (ADC). The design is primarily targeted for upstream DOCSIS 3.1 receiver (...)
Design guide: PDF
Schematic: PDF
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VQFN (RMP) 72 View options

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