Product details

Sample rate (Max) (MSPS) 1000 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 70.9 ENOB (Bits) 11.5 SFDR (dB) 90 Operating temperature range (C) -40 to 85 Input buffer Yes
Sample rate (Max) (MSPS) 1000 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 70.9 ENOB (Bits) 11.5 SFDR (dB) 90 Operating temperature range (C) -40 to 85 Input buffer Yes
VQFNP (RMP) 72 100 mm² 10 x 10
  • 16-bit resolution, dual-channel, 1-GSPS ADC
  • Noise floor: –159 dBFS/Hz
  • Spectral performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 70 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 86 dBc (including interleaving tones)
    • SFDR: 89 dBc (except HD2, HD3, and interleaving tones)
  • Spectral performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 67.5 dBFS
    • NSD: –154.5 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (except HD2, HD3, and interleaving tones)
  • Channel isolation: 100 dBc at fIN = 170 MHz
  • Input full-scale: 1.9 VPP
  • Input bandwidth (3 dB): 1.2 GHz
  • On-chip dither
  • Integrated wideband DDC block
  • JESD204B interface with subclass 1 support:
    • 2 lanes per ADC at 10.0 Gbps
    • 4 lanes per ADC at 5.0 Gbps
    • Support for multi-chip synchronization
  • Power dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-pin VQFNP (10 mm × 10 mm)
  • 16-bit resolution, dual-channel, 1-GSPS ADC
  • Noise floor: –159 dBFS/Hz
  • Spectral performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 70 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 86 dBc (including interleaving tones)
    • SFDR: 89 dBc (except HD2, HD3, and interleaving tones)
  • Spectral performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 67.5 dBFS
    • NSD: –154.5 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (except HD2, HD3, and interleaving tones)
  • Channel isolation: 100 dBc at fIN = 170 MHz
  • Input full-scale: 1.9 VPP
  • Input bandwidth (3 dB): 1.2 GHz
  • On-chip dither
  • Integrated wideband DDC block
  • JESD204B interface with subclass 1 support:
    • 2 lanes per ADC at 10.0 Gbps
    • 4 lanes per ADC at 5.0 Gbps
    • Support for multi-chip synchronization
  • Power dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-pin VQFNP (10 mm × 10 mm)

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.





The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.





Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 9
Type Title Date
* Data sheet ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter datasheet (Rev. D) 17 Apr 2019
Technical article Keys to quick success using high-speed data converters 13 Oct 2020
Technical article How to achieve fast frequency hopping 03 Mar 2019
User guide HSDC Pro with Xilinx KCU105 01 Mar 2017
Technical article RF sampling: Learning more about latency 09 Feb 2017
Technical article Why phase noise matters in RF sampling converters 28 Nov 2016
Application note JESD204B over optical fiber enables new architecture for phased-array radar 26 Jan 2016
User guide ADS54J60EVM User's Guide (Rev. A) 11 Jan 2016
User guide TSW54J60 Evaluation Module User's Guide (Rev. A) 21 Sep 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADS54J60EVM — ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter Evaluation Module

The ADS54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60 and LMK04828 clock jitter cleaner. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface (...)

In stock
Limit: 3
Evaluation board

TSW54J60EVM — 400MHz Input Bandwidth Digitizer: Dual 16-Bit, 1-GSPS ADC and Wideband Fixed or Variable Gain Amps

The TSW54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60, LMH3401, LMH6401 and LMK04828 devices. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

In stock
Limit: 3
Evaluation board

ABACO-3P-FMC120 — Abaco Systems® 4-channel 16-bit ADC/DAC input/output FPGA mezzanine card

The Abaco FMC120 provides four 16-bit analog-to-digital converters (ADCs) and four 16-bit digital-to-analog converters (DACs). The module highlights two products from Texas Instruments: the ADS54J60 two-channel, 16-bit, 1-GSPS ADC (two) and the DAC39J84 four-channel, 16-bit, 2.8-GSPS DAC (one) in a (...)

From: Abaco Systems
Firmware

TI-JESD204-IP — JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters

The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Support software

DATACONVERTERPRO-SW — High-speed data converter pro software

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter and analog front-end (AFE) platforms. Designed to support the entire TSW14xxx series of data-capture and pattern-generation cards (...)
Simulation model

ADS54J20/40/60 IBIS MODEL

SBAM205.ZIP (46 KB) - IBIS Model
Simulation model

ADS54J20/40/60 IBIS-AMI Model

SBAM325.ZIP (5519 KB) - IBIS-AMI Model
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Reference designs

TIDA-00823 — 16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Fixed Gain Amplifier

This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
Reference designs

TIDA-00822 — 16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Variable Gain Amplifier

This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
Package Pins Download
VQFN (RMP) 72 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos