ADS54J60

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Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter (ADC)

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Product details

Parameters

Sample rate (Max) (MSPS) 1000 Resolution (Bits) 16 Number of input channels 2 Interface type JESD204B Analog input BW (MHz) 1200 Features Ultra High Speed Rating Catalog Input range (Vp-p) 1.9 Power consumption (Typ) (mW) 2700 Architecture Pipeline SNR (dB) 70.9 ENOB (Bits) 11.5 SFDR (dB) 90 Operating temperature range (C) -40 to 85 Input buffer Yes open-in-new Find other High-speed ADCs (>10MSPS)

Package | Pins | Size

VQFNP (RMP) 72 100 mm² 10 x 10 open-in-new Find other High-speed ADCs (>10MSPS)

Features

  • 16-bit resolution, dual-channel, 1-GSPS ADC
  • Noise floor: –159 dBFS/Hz
  • Spectral performance (fIN = 170 MHz at –1 dBFS):
    • SNR: 70 dBFS
    • NSD: –157 dBFS/Hz
    • SFDR: 86 dBc (including interleaving tones)
    • SFDR: 89 dBc (except HD2, HD3, and interleaving tones)
  • Spectral performance (fIN = 350 MHz at –1 dBFS):
    • SNR: 67.5 dBFS
    • NSD: –154.5 dBFS/Hz
    • SFDR: 75 dBc
    • SFDR: 85 dBc (except HD2, HD3, and interleaving tones)
  • Channel isolation: 100 dBc at fIN = 170 MHz
  • Input full-scale: 1.9 VPP
  • Input bandwidth (3 dB): 1.2 GHz
  • On-chip dither
  • Integrated wideband DDC block
  • JESD204B interface with subclass 1 support:
    • 2 lanes per ADC at 10.0 Gbps
    • 4 lanes per ADC at 5.0 Gbps
    • Support for multi-chip synchronization
  • Power dissipation: 1.35 W/Ch at 1 GSPS
  • Package: 72-pin VQFNP (10 mm × 10 mm)

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open-in-new Find other High-speed ADCs (>10MSPS)

Description

The ADS54J60 is a low-power, wide-bandwidth, 16-bit, 1.0-GSPS, dual-channel, analog-to-digital converter (ADC). Designed for high signal-to-noise ratio (SNR), the device delivers a noise floor of –159 dBFS/Hz for applications aiming for highest dynamic range over a wide instantaneous bandwidth. The device supports the JESD204B serial interface with data rates up to 10 Gbps, supporting two or four lanes per ADC. The buffered analog input provides uniform input impedance across a wide frequency range while minimizing sample-and-hold glitch energy. Each ADC channel optionally can be connected to a wideband digital down-converter (DDC) block. The ADS54J60 provides excellent spurious-free dynamic range (SFDR) over a large input frequency range with very low power consumption.

The JESD204B interface reduces the number of interface lines, allowing high system integration density. An internal phase-locked loop (PLL) multiplies the ADC sampling clock to derive the bit clock that is used to serialize the 16-bit data from each channel.





open-in-new Find other High-speed ADCs (>10MSPS)
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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 9
Type Title Date
* Datasheet ADS54J60 Dual-Channel, 16-Bit, 1.0-GSPS Analog-to-Digital Converter datasheet (Rev. D) Apr. 17, 2019
Technical articles Keys to quick success using high-speed data converters Oct. 13, 2020
Technical articles How to achieve fast frequency hopping Mar. 03, 2019
User guide HSDC Pro with Xilinx KCU105 Mar. 01, 2017
Technical articles RF sampling: Learning more about latency Feb. 09, 2017
Technical articles Why phase noise matters in RF sampling converters Nov. 28, 2016
Application note JESD204B over optical fiber enables new architecture for phased-array radar Jan. 26, 2016
User guide ADS54J60EVM User's Guide (Rev. A) Jan. 11, 2016
User guide TSW54J60 Evaluation Module User's Guide (Rev. A) Sep. 21, 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
Description

The ADS54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60 and LMK04828 clock jitter cleaner. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface (...)

Features
  • Flexible transformer coupled analog input to allow for a variety of sources and frequencies
  • Easy to use software GUI to configure the ADS54J60 and LMK04828 for a variety of configurations through a USB interface
  • Quickly evaluate ADC performance through High Speed Data Converter Pro software
  • Simple (...)
EVALUATION BOARD Download
899
Description

The TSW54J60EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J60, LMH3401, LMH6401 and LMK04828 devices. The ADS54J60 is a low power, 16-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B (...)

Features
  • Flexible transformer coupled analog input on the LMH6401 path to allow for a variety of sources and frequencies
  • Options for AC or DC coupling, single-ended or differential inputs
  • Easy to use software GUI to configure the ADS54J60, LMH6401 and LMK04828 for a variety of configurations through a USB (...)
EVALUATION BOARD Download
Description

The Abaco FMC120 provides four 16-bit analog-to-digital converters (ADCs) and four 16-bit digital-to-analog converters (DACs). The module highlights two products from Texas Instruments: the ADS54J60 two-channel, 16-bit, 1-GSPS ADC (two) and the DAC39J84 four-channel, 16-bit, 2.8-GSPS DAC (one) in a (...)

Software development

FIRMWARE Download
JESD204 Rapid Design IP for FPGAs connected to TI high-speed data converters
TI-JESD204-IP The JESD204 rapid design IP has been designed to enable FPGA engineers to achieve an accelerated path to a working JESD204 system. The IP has been architected in a way that downstream digital processing and other application logic are isolated from most of the performance- and timing-critical (...)
Features
  • Compatible with JEDEC JESD204a/b/c protocols
  • Supports subclass 1 deterministic latency and multidevice synchronization
  • Supported lane rates
    • Up to 16.375 Gbps in 8b/10b mode
    • Up to 20 Gbps in 64b/66b mode
  • Supports all protocol related error detection and reporting features
  • Integrated transport layer (...)

Design tools & simulation

SIMULATION MODEL Download
SBAM205.ZIP (46 KB) - IBIS Model
SIMULATION MODEL Download
SBAM325.ZIP (5519 KB) - IBIS-AMI Model
SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)

Reference designs

REFERENCE DESIGNS Download
16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Fixed Gain Amplifier
TIDA-00823 — This reference design discusses the use and performance of the Ultra-Wideband, Fixed-gain high-speed amplifier, the LMH3401 to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
document-generic Schematic
REFERENCE DESIGNS Download
16-Bit 1-GSPS Digitizer Reference Design with AC and DC Coupled Variable Gain Amplifier
TIDA-00822 This reference design discusses the use and performance of the Digital Variable-Gain high-speed amplifier, the LMH6401, to drive the high-speed analog-to-digital converter (ADC), the ADS54J60 device. Different options for common-mode voltages, power supplies, and interfaces are discussed and (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
VQFN (RMP) 72 View options

Ordering & quality

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  • MTBF/FIT estimates
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  • Qualification summary
  • Ongoing reliability monitoring

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