SPRUJ53 April   2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1

 

  1.   1
  2.   Read This First
    1.     About This Manual
    2.     Notational Conventions
    3.     Glossary
    4.     Related Documentation From Texas Instruments
    5.     Support Resources
    6.     Trademarks
  3. 1 C2000™ Microcontrollers Software Support
    1. 1.1 Introduction
    2. 1.2 C2000Ware Structure
    3. 1.3 Documentation
    4. 1.4 Devices
    5. 1.5 Libraries
    6. 1.6 Code Composer Studio™ Integrated Development Environment (IDE)
    7. 1.7 SysConfig and PinMUX Tool
  4. 2 C28x Processor
    1. 2.1 Introduction
    2. 2.2 C28X Related Collateral
    3. 2.3 Features
    4. 2.4 Floating-Point Unit
    5. 2.5 Trigonometric Math Unit (TMU)
    6. 2.6 VCRC Unit
  5. 3 System Control and Interrupts
    1. 3.1  Introduction
      1. 3.1.1 SYSCTL Related Collateral
      2. 3.1.2 LOCK Protection on System Configuration Registers
      3. 3.1.3 EALLOW Protection
    2. 3.2  Power Management
    3. 3.3  Device Identification and Configuration Registers
    4. 3.4  Resets
      1. 3.4.1  Reset Sources
      2. 3.4.2  External Reset (XRS)
      3. 3.4.3  Simulate External Reset (SIMRESET. XRS)
      4. 3.4.4  Power-On Reset (POR)
      5. 3.4.5  Brown-Out Reset (BOR)
      6. 3.4.6  Debugger Reset (SYSRS)
      7. 3.4.7  Simulate CPU Reset
      8. 3.4.8  Watchdog Reset (WDRS)
      9. 3.4.9  NMI Watchdog Reset (NMIWDRS)
      10. 3.4.10 DCSM Safe Code Copy Reset (SCCRESET)
    5. 3.5  Peripheral Interrupts
      1. 3.5.1 Interrupt Concepts
      2. 3.5.2 Interrupt Architecture
        1. 3.5.2.1 Peripheral Stage
        2. 3.5.2.2 PIE Stage
        3. 3.5.2.3 CPU Stage
      3. 3.5.3 Interrupt Entry Sequence
      4. 3.5.4 Configuring and Using Interrupts
        1. 3.5.4.1 Enabling Interrupts
        2. 3.5.4.2 Handling Interrupts
        3. 3.5.4.3 Disabling Interrupts
        4. 3.5.4.4 Nesting Interrupts
        5. 3.5.4.5 Vector Address Validity Check
      5. 3.5.5 PIE Channel Mapping
      6. 3.5.6 PIE Interrupt Priority
        1. 3.5.6.1 Channel Priority
        2. 3.5.6.2 Group Priority
      7. 3.5.7 System Error
      8. 3.5.8 Vector Tables
    6. 3.6  Exceptions and Non-Maskable Interrupts
      1. 3.6.1 Configuring and Using NMIs
      2. 3.6.2 Emulation Considerations
      3. 3.6.3 NMI Sources
        1. 3.6.3.1 Missing Clock Detection
        2. 3.6.3.2 RAM Uncorrectable Error
        3. 3.6.3.3 Flash Uncorrectable ECC Error
        4. 3.6.3.4 Software-Forced Error
        5. 3.6.3.5 ERAD NMI
      4. 3.6.4 Illegal Instruction Trap (ITRAP)
      5. 3.6.5 ERRORSTS Pin
    7. 3.7  Clocking
      1. 3.7.1  Clock Sources
        1. 3.7.1.1 Primary Internal Oscillator (INTOSC2)
        2. 3.7.1.2 Backup Internal Oscillator (INTOSC1)
        3. 3.7.1.3 Auxiliary Clock Input (AUXCLKIN)
        4. 3.7.1.4 External Oscillator (XTAL)
      2. 3.7.2  Derived Clocks
        1. 3.7.2.1 Oscillator Clock (OSCCLK)
        2. 3.7.2.2 System PLL Output Clock (PLLRAWCLK)
      3. 3.7.3  Device Clock Domains
        1. 3.7.3.1 System Clock (PLLSYSCLK)
        2. 3.7.3.2 CPU Clock (CPUCLK)
        3. 3.7.3.3 CPU Subsystem Clock (SYSCLK and PERx.SYSCLK)
        4. 3.7.3.4 Low-Speed Peripheral Clock (LSPCLK and PERx.LSPCLK)
        5. 3.7.3.5 USB Bit Clock
        6. 3.7.3.6 CAN Bit Clock
        7. 3.7.3.7 CLB Clock
        8. 3.7.3.8 LIN Clock
        9. 3.7.3.9 CPU Timer2 Clock (TIMER2CLK)
      4. 3.7.4  XCLKOUT
      5. 3.7.5  Clock Connectivity
      6. 3.7.6  Clock Source and PLL Setup
      7. 3.7.7  Using an External Crystal or Resonator
        1. 3.7.7.1 X1/X2 Precondition Circuit
      8. 3.7.8  Using an External Oscillator
      9. 3.7.9  Choosing PLL Settings
      10. 3.7.10 System Clock Setup
      11. 3.7.11 SYS PLL Bypass
      12. 3.7.12 Clock (OSCCLK) Failure Detection
        1. 3.7.12.1 Missing Clock Detection
    8. 3.8  32-Bit CPU Timers 0/1/2
    9. 3.9  Watchdog Timer
      1. 3.9.1 Servicing the Watchdog Timer
      2. 3.9.2 Minimum Window Check
      3. 3.9.3 Watchdog Reset or Watchdog Interrupt Mode
      4. 3.9.4 Watchdog Operation in Low-Power Modes
      5. 3.9.5 Emulation Considerations
    10. 3.10 Low-Power Modes
      1. 3.10.1 Clock-Gating Low-Power Modes
      2. 3.10.2 IDLE
      3. 3.10.3 STANDBY
      4. 3.10.4 HALT
    11. 3.11 Memory Controller Module
      1. 3.11.1 Functional Description
        1. 3.11.1.1  Dedicated RAM (Mx RAM)
        2. 3.11.1.2  Local Shared RAM (LSx RAM)
        3. 3.11.1.3  Global Shared RAM (GSx RAM)
        4. 3.11.1.4  CAN Message RAM
        5. 3.11.1.5  CLA-CPU Message RAM
        6. 3.11.1.6  CLA-DMA Message RAM
        7. 3.11.1.7  Access Arbitration
        8. 3.11.1.8  Access Protection
          1. 3.11.1.8.1 CPU Fetch Protection
          2. 3.11.1.8.2 CPU Write Protection
          3. 3.11.1.8.3 CPU Read Protection
          4. 3.11.1.8.4 CLA Fetch Protection
          5. 3.11.1.8.5 CLA Write Protection
          6. 3.11.1.8.6 CLA Read Protection
          7. 3.11.1.8.7 DMA Write Protection
          8. 3.11.1.8.8 NNPU Write Protection
        9. 3.11.1.9  Memory Error Detection, Correction, and Error Handling
          1. 3.11.1.9.1 Error Detection and Correction
          2. 3.11.1.9.2 Error Handling
        10. 3.11.1.10 Application Test Hooks for Error Detection and Correction
        11. 3.11.1.11 RAM Initialization
    12. 3.12 JTAG
      1. 3.12.1 JTAG Noise and TAP_STATUS
    13. 3.13 Live Firmware Update
      1. 3.13.1 LFU Background
      2. 3.13.2 LFU Switchover Steps
      3. 3.13.3 Device Features Supporting LFU
        1. 3.13.3.1 Multi-Bank Flash
        2. 3.13.3.2 PIE Vector Table Swap
        3. 3.13.3.3 LS0/LS1 RAM Memory Swap
          1. 3.13.3.3.1 Applicability to CLA LFU
      4. 3.13.4 LFU Switchover
      5. 3.13.5 LFU Resources
    14. 3.14 System Control Register Configuration Restrictions
    15. 3.15 Software
      1. 3.15.1  SYSCTL Registers to Driverlib Functions
      2. 3.15.2  CPUTIMER Registers to Driverlib Functions
      3. 3.15.3  MEMCFG Registers to Driverlib Functions
      4. 3.15.4  PIE Registers to Driverlib Functions
      5. 3.15.5  NMI Registers to Driverlib Functions
      6. 3.15.6  XINT Registers to Driverlib Functions
      7. 3.15.7  WWD Registers to Driverlib Functions
      8. 3.15.8  SYSCTL Examples
        1. 3.15.8.1 Missing clock detection (MCD)
        2. 3.15.8.2 XCLKOUT (External Clock Output) Configuration
      9. 3.15.9  TIMER Examples
        1. 3.15.9.1 CPU Timers
        2. 3.15.9.2 CPU Timers
      10. 3.15.10 MEMCFG Examples
        1. 3.15.10.1 Correctable & Uncorrectable Memory Error Handling
      11. 3.15.11 INTERRUPT Examples
        1. 3.15.11.1 External Interrupts (ExternalInterrupt)
        2. 3.15.11.2 Multiple interrupt handling of I2C, SCI & SPI Digital Loopback
        3. 3.15.11.3 CPU Timer Interrupt Software Prioritization
        4. 3.15.11.4 EPWM Real-Time Interrupt
      12. 3.15.12 LPM Examples
        1. 3.15.12.1 Low Power Modes: Device Idle Mode and Wakeup using GPIO
        2. 3.15.12.2 Low Power Modes: Device Idle Mode and Wakeup using Watchdog
        3. 3.15.12.3 Low Power Modes: Device Standby Mode and Wakeup using GPIO
        4. 3.15.12.4 Low Power Modes: Device Standby Mode and Wakeup using Watchdog
        5. 3.15.12.5 Low Power Modes: Halt Mode and Wakeup using GPIO
        6. 3.15.12.6 Low Power Modes: Halt Mode and Wakeup
      13. 3.15.13 WATCHDOG Examples
        1. 3.15.13.1 Watchdog
    16. 3.16 SYSCTRL Registers
      1. 3.16.1  SYSCTRL Base Address Table
      2. 3.16.2  CPUTIMER_REGS Registers
      3. 3.16.3  PIE_CTRL_REGS Registers
      4. 3.16.4  NMI_INTRUPT_REGS Registers
      5. 3.16.5  XINT_REGS Registers
      6. 3.16.6  SYNC_SOC_REGS Registers
      7. 3.16.7  DMA_CLA_SRC_SEL_REGS Registers
      8. 3.16.8  LFU_REGS Registers
      9. 3.16.9  DEV_CFG_REGS Registers
      10. 3.16.10 CLK_CFG_REGS Registers
      11. 3.16.11 CPU_SYS_REGS Registers
      12. 3.16.12 SYS_STATUS_REGS Registers
      13. 3.16.13 PERIPH_AC_REGS Registers
      14. 3.16.14 MEM_CFG_REGS Registers
      15. 3.16.15 ACCESS_PROTECTION_REGS Registers
      16. 3.16.16 MEMORY_ERROR_REGS Registers
      17. 3.16.17 TEST_ERROR_REGS Registers
      18. 3.16.18 UID_REGS Registers
  6. 4 ROM Code and Peripheral Booting
    1. 4.1 Introduction
      1. 4.1.1 ROM Related Collateral
    2. 4.2 Device Boot Sequence
    3. 4.3 Device Boot Modes
      1. 4.3.1 Default Boot Modes
      2. 4.3.2 Custom Boot Modes
    4. 4.4 Device Boot Configurations
      1. 4.4.1 Configuring Boot Mode Pins
      2. 4.4.2 Configuring Boot Mode Table Options
      3. 4.4.3 Boot Mode Example Use Cases
        1. 4.4.3.1 Zero Boot Mode Select Pins
        2. 4.4.3.2 One Boot Mode Select Pin
        3. 4.4.3.3 Three Boot Mode Select Pins
    5. 4.5 Device Boot Flow Diagrams
      1. 4.5.1 Boot Flow
      2. 4.5.2 Emulation Boot Flow
      3. 4.5.3 Standalone Boot Flow
    6. 4.6 Device Reset and Exception Handling
      1. 4.6.1 Reset Causes and Handling
      2. 4.6.2 Exceptions and Interrupts Handling
    7. 4.7 Boot ROM Description
      1. 4.7.1  Boot ROM Configuration Registers
        1. 4.7.1.1 MPOST Configuration
      2. 4.7.2  Entry Points
      3. 4.7.3  Wait Points
      4. 4.7.4  Secure Flash Boot
        1. 4.7.4.1 Secure Flash CPU1 Linker File Example
      5. 4.7.5  Firmware Update (FWU) Flash Boot
      6. 4.7.6  Memory Maps
        1. 4.7.6.1 Boot ROM Memory Maps
        2. 4.7.6.2 CLA Data ROM Memory Maps
        3. 4.7.6.3 Reserved RAM Memory Maps
      7. 4.7.7  ROM Tables
      8. 4.7.8  Boot Modes and Loaders
        1. 4.7.8.1 Boot Modes
          1. 4.7.8.1.1 Flash Boot
          2. 4.7.8.1.2 RAM Boot
          3. 4.7.8.1.3 Wait Boot
        2. 4.7.8.2 Bootloaders
          1. 4.7.8.2.1 SCI Boot Mode
          2. 4.7.8.2.2 SPI Boot Mode
          3. 4.7.8.2.3 I2C Boot Mode
          4. 4.7.8.2.4 Parallel Boot Mode
          5. 4.7.8.2.5 CAN Boot Mode (MCAN in non-FD mode)
          6. 4.7.8.2.6 CAN-FD Boot Mode
          7. 4.7.8.2.7 USB Boot Mode
      9. 4.7.9  GPIO Assignments
      10. 4.7.10 Secure ROM Function APIs
      11. 4.7.11 Clock Initializations
      12. 4.7.12 Boot Status Information
        1. 4.7.12.1 Booting Status
        2. 4.7.12.2 Boot Mode and MPOST (Memory Power On Self-Test) Status
      13. 4.7.13 ROM Version
    8. 4.8 Application Notes for Using the Bootloaders
      1. 4.8.1 Bootloader Data Stream Structure
        1. 4.8.1.1 Data Stream Structure 8-bit
      2. 4.8.2 The C2000 Hex Utility
        1. 4.8.2.1 HEX2000.exe Command Syntax
    9. 4.9 Software
      1. 4.9.1 BOOT Examples
  7. 5 Dual Code Security Module (DCSM)
    1. 5.1 Introduction
      1. 5.1.1 DCSM Related Collateral
    2. 5.2 Functional Description
      1. 5.2.1 CSM Passwords
      2. 5.2.2 Emulation Code Security Logic (ECSL)
      3. 5.2.3 CPU Secure Logic
      4. 5.2.4 Execute-Only Protection
      5. 5.2.5 Password Lock
      6. 5.2.6 JTAGLOCK
      7. 5.2.7 Link Pointer and Zone Select
      8. 5.2.8 C Code Example to Get Zone Select Block Addr for Zone1
    3. 5.3 Flash and OTP Erase/Program
    4. 5.4 Secure Copy Code
    5. 5.5 SecureCRC
    6. 5.6 CSM Impact on Other On-Chip Resources
    7. 5.7 Incorporating Code Security in User Applications
      1. 5.7.1 Environments That Require Security Unlocking
      2. 5.7.2 CSM Password Match Flow
      3. 5.7.3 C Code Example to Unsecure C28x Zone1
      4. 5.7.4 C Code Example to Resecure C28x Zone1
      5. 5.7.5 Environments That Require ECSL Unlocking
      6. 5.7.6 ECSL Password Match Flow
      7. 5.7.7 ECSL Disable Considerations for any Zone
        1. 5.7.7.1 C Code Example to Disable ECSL for C28x Zone1
      8. 5.7.8 Device Unique ID
    8. 5.8 Software
      1. 5.8.1 DCSM Registers to Driverlib Functions
      2. 5.8.2 DCSM Examples
        1. 5.8.2.1 Empty DCSM Tool Example
    9. 5.9 DCSM Registers
      1. 5.9.1 DCSM Base Address Table
      2. 5.9.2 DCSM_Z1_REGS Registers
      3. 5.9.3 DCSM_Z2_REGS Registers
      4. 5.9.4 DCSM_COMMON_REGS Registers
      5. 5.9.5 DCSM_Z1_OTP Registers
      6. 5.9.6 DCSM_Z2_OTP Registers
  8. 6 Flash Module
    1. 6.1  Introduction to Flash and OTP Memory
      1. 6.1.1 FLASH Related Collateral
      2. 6.1.2 Features
      3. 6.1.3 Flash Tools
      4. 6.1.4 Default Flash Configuration
    2. 6.2  Flash Bank, OTP, and Pump
    3. 6.3  Flash Wrapper
    4. 6.4  Flash and OTP Memory Performance
    5. 6.5  Flash Read Interface
      1. 6.5.1 C28x-Flash Read Interface
        1. 6.5.1.1 Standard Read Mode
        2. 6.5.1.2 Prefetch Mode
        3. 6.5.1.3 Data Cache
        4. 6.5.1.4 Flash Read Operation
    6. 6.6  Flash Erase and Program
      1. 6.6.1 Erase
      2. 6.6.2 Program
      3. 6.6.3 Verify
    7. 6.7  Error Correction Code (ECC) Protection
      1. 6.7.1 Single-Bit Data Error
      2. 6.7.2 Uncorrectable Error
      3. 6.7.3 Mechanism to Check the Correctness of ECC Logic
    8. 6.8  Reserved Locations Within Flash and OTP
    9. 6.9  Migrating an Application from RAM to Flash
    10. 6.10 Procedure to Change the Flash Control Registers
    11. 6.11 Software
      1. 6.11.1 FLASH Registers to Driverlib Functions
      2. 6.11.2 FLASH Examples
        1. 6.11.2.1 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
        2. 6.11.2.2 Flash Programming with AutoECC, DataAndECC, DataOnly and EccOnly
    12. 6.12 FLASH Registers
      1. 6.12.1 FLASH Base Address Table
      2. 6.12.2 FLASH_CTRL_REGS Registers
      3. 6.12.3 FLASH_ECC_REGS Registers
  9. 7 Control Law Accelerator (CLA)
    1. 7.1 Introduction
      1. 7.1.1 Features
      2. 7.1.2 CLA Related Collateral
      3. 7.1.3 Block Diagram
    2. 7.2 CLA Interface
      1. 7.2.1 CLA Memory
      2. 7.2.2 CLA Memory Bus
      3. 7.2.3 Shared Peripherals and EALLOW Protection
      4. 7.2.4 CLA Tasks and Interrupt Vectors
    3. 7.3 CLA, DMA, and CPU Arbitration
      1. 7.3.1 CLA Message RAM
      2. 7.3.2 CLA Program Memory
      3. 7.3.3 CLA Data Memory
      4. 7.3.4 Peripheral Registers (ePWM, HRPWM, Comparator)
    4. 7.4 CLA Configuration and Debug
      1. 7.4.1 Building a CLA Application
      2. 7.4.2 Typical CLA Initialization Sequence
      3. 7.4.3 Debugging CLA Code
        1. 7.4.3.1 Breakpoint Support (MDEBUGSTOP)
      4. 7.4.4 CLA Illegal Opcode Behavior
      5. 7.4.5 Resetting the CLA
    5. 7.5 Pipeline
      1. 7.5.1 Pipeline Overview
      2. 7.5.2 CLA Pipeline Alignment
        1. 7.5.2.1 Code Fragment For MBCNDD, MCCNDD, or MRCNDD
        2.       358
        3. 7.5.2.2 Code Fragment for Loading MAR0 or MAR1
        4.       360
        5. 7.5.2.3 ADC Early Interrupt to CLA Response
      3. 7.5.3 Parallel Instructions
        1. 7.5.3.1 Math Operation with Parallel Load
        2. 7.5.3.2 Multiply with Parallel Add
      4. 7.5.4 CLA Task Execution Latency
    6. 7.6 Software
      1. 7.6.1 CLA Registers to Driverlib Functions
      2. 7.6.2 CLA Examples
        1. 7.6.2.1 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        2. 7.6.2.2 CLA arcsine(x) using a lookup table (cla_asin_cpu01)
        3. 7.6.2.3 CLA arctangent(x) using a lookup table (cla_atan_cpu01)
        4. 7.6.2.4 CLA background nesting task
        5. 7.6.2.5 Controlling PWM output using CLA
        6. 7.6.2.6 Just-in-time ADC sampling with CLA
        7. 7.6.2.7 Optimal offloading of control algorithms to CLA
        8. 7.6.2.8 Handling shared resources across C28x and CLA
    7. 7.7 Instruction Set
      1. 7.7.1 Instruction Descriptions
      2. 7.7.2 Addressing Modes and Encoding
      3. 7.7.3 Instructions
        1.       MABSF32 MRa, MRb
        2.       MADD32 MRa, MRb, MRc
        3.       MADDF32 MRa, #16FHi, MRb
        4.       MADDF32 MRa, MRb, #16FHi
        5.       MADDF32 MRa, MRb, MRc
        6.       MADDF32 MRd, MRe, MRf||MMOV32 mem32, MRa
        7.       MADDF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        8.       MAND32 MRa, MRb, MRc
        9.       MASR32 MRa, #SHIFT
        10.       MBCNDD 16BitDest {, CNDF}
        11.       MCCNDD 16BitDest {, CNDF}
        12.       MCMP32 MRa, MRb
        13.       MCMPF32 MRa, MRb
        14.       MCMPF32 MRa, #16FHi
        15.       MDEBUGSTOP
        16.       MEALLOW
        17.       MEDIS
        18.       MEINVF32 MRa, MRb
        19.       MEISQRTF32 MRa, MRb
        20.       MF32TOI16 MRa, MRb
        21.       MF32TOI16R MRa, MRb
        22.       MF32TOI32 MRa, MRb
        23.       MF32TOUI16 MRa, MRb
        24.       MF32TOUI16R MRa, MRb
        25.       MF32TOUI32 MRa, MRb
        26.       MFRACF32 MRa, MRb
        27.       MI16TOF32 MRa, MRb
        28.       MI16TOF32 MRa, mem16
        29.       MI32TOF32 MRa, mem32
        30.       MI32TOF32 MRa, MRb
        31.       MLSL32 MRa, #SHIFT
        32.       MLSR32 MRa, #SHIFT
        33.       MMACF32 MR3, MR2, MRd, MRe, MRf ||MMOV32 MRa, mem32
        34.       MMAXF32 MRa, MRb
        35.       MMAXF32 MRa, #16FHi
        36.       MMINF32 MRa, MRb
        37.       MMINF32 MRa, #16FHi
        38.       MMOV16 MARx, MRa, #16I
        39.       MMOV16 MARx, mem16
        40.       MMOV16 mem16, MARx
        41.       MMOV16 mem16, MRa
        42.       MMOV32 mem32, MRa
        43.       MMOV32 mem32, MSTF
        44.       MMOV32 MRa, mem32 {, CNDF}
        45.       MMOV32 MRa, MRb {, CNDF}
        46.       MMOV32 MSTF, mem32
        47.       MMOVD32 MRa, mem32
        48.       MMOVF32 MRa, #32F
        49.       MMOVI16 MARx, #16I
        50.       MMOVI32 MRa, #32FHex
        51.       MMOVIZ MRa, #16FHi
        52.       MMOVZ16 MRa, mem16
        53.       MMOVXI MRa, #16FLoHex
        54.       MMPYF32 MRa, MRb, MRc
        55.       MMPYF32 MRa, #16FHi, MRb
        56.       MMPYF32 MRa, MRb, #16FHi
        57.       MMPYF32 MRa, MRb, MRc||MADDF32 MRd, MRe, MRf
        58.       MMPYF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        59.       MMPYF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        60.       MMPYF32 MRa, MRb, MRc ||MSUBF32 MRd, MRe, MRf
        61.       MNEGF32 MRa, MRb{, CNDF}
        62.       MNOP
        63.       MOR32 MRa, MRb, MRc
        64.       MRCNDD {CNDF}
        65.       MSETFLG FLAG, VALUE
        66.       MSTOP
        67.       MSUB32 MRa, MRb, MRc
        68.       MSUBF32 MRa, MRb, MRc
        69.       MSUBF32 MRa, #16FHi, MRb
        70.       MSUBF32 MRd, MRe, MRf ||MMOV32 MRa, mem32
        71.       MSUBF32 MRd, MRe, MRf ||MMOV32 mem32, MRa
        72.       MSWAPF MRa, MRb {, CNDF}
        73.       MTESTTF CNDF
        74.       MUI16TOF32 MRa, mem16
        75.       MUI16TOF32 MRa, MRb
        76.       MUI32TOF32 MRa, mem32
        77.       MUI32TOF32 MRa, MRb
        78.       MXOR32 MRa, MRb, MRc
    8. 7.8 CLA Registers
      1. 7.8.1 CLA Base Address Table
      2. 7.8.2 CLA_ONLY_REGS Registers
      3. 7.8.3 CLA_SOFTINT_REGS Registers
      4. 7.8.4 CLA_REGS Registers
  10. 8 Dual-Clock Comparator (DCC)
    1. 8.1 Introduction
      1. 8.1.1 Features
      2. 8.1.2 Block Diagram
    2. 8.2 Module Operation
      1. 8.2.1 Configuring DCC Counters
      2. 8.2.2 Single-Shot Measurement Mode
      3. 8.2.3 Continuous Monitoring Mode
      4. 8.2.4 Error Conditions
    3. 8.3 Interrupts
    4. 8.4 Software
      1. 8.4.1 DCC Registers to Driverlib Functions
      2. 8.4.2 DCC Examples
        1. 8.4.2.1 DCC Single shot Clock verification
        2. 8.4.2.2 DCC Single shot Clock measurement
        3. 8.4.2.3 DCC Continuous clock monitoring
        4. 8.4.2.4 DCC Continuous clock monitoring
        5. 8.4.2.5 DCC Detection of clock failure
    5. 8.5 DCC Registers
      1. 8.5.1 DCC Base Address Table
      2. 8.5.2 DCC_REGS Registers
  11. 9 General-Purpose Input/Output (GPIO)
    1. 9.1  Introduction
      1. 9.1.1 GPIO Related Collateral
    2. 9.2  Configuration Overview
    3. 9.3  Digital Inputs on ADC Pins (AIOs)
    4. 9.4  Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 9.5  Digital General-Purpose I/O Control
    6. 9.6  Input Qualification
      1. 9.6.1 No Synchronization (Asynchronous Input)
      2. 9.6.2 Synchronization to SYSCLKOUT Only
      3. 9.6.3 Qualification Using a Sampling Window
    7. 9.7  USB Signals
    8. 9.8  PMBUS and I2C Signals
    9. 9.9  GPIO and Peripheral Muxing
      1. 9.9.1 GPIO Muxing
      2. 9.9.2 Peripheral Muxing
    10. 9.10 Internal Pullup Configuration Requirements
    11. 9.11 Software
      1. 9.11.1 GPIO Registers to Driverlib Functions
      2. 9.11.2 GPIO Examples
        1. 9.11.2.1 Device GPIO Setup
        2. 9.11.2.2 Device GPIO Toggle
        3. 9.11.2.3 Device GPIO Interrupt
        4. 9.11.2.4 External Interrupt (XINT)
      3. 9.11.3 LED Examples
    12. 9.12 GPIO Registers
      1. 9.12.1 GPIO Base Address Table
      2. 9.12.2 GPIO_CTRL_REGS Registers
      3. 9.12.3 GPIO_DATA_REGS Registers
      4. 9.12.4 GPIO_DATA_READ_REGS Registers
  12. 10Crossbar (X-BAR)
    1. 10.1 Input X-BAR and CLB Input X-BAR
      1. 10.1.1 CLB Input X-BAR
    2. 10.2 ePWM, CLB, and GPIO Output X-BAR
      1. 10.2.1 ePWM X-BAR
        1. 10.2.1.1 ePWM X-BAR Architecture
      2. 10.2.2 CLB X-BAR
        1. 10.2.2.1 CLB X-BAR Architecture
      3. 10.2.3 GPIO Output X-BAR
        1. 10.2.3.1 GPIO Output X-BAR Architecture
      4. 10.2.4 X-BAR Flags
    3. 10.3 Software
      1. 10.3.1 XBAR Registers to Driverlib Functions
      2. 10.3.2 INPUTXBAR Registers to Driverlib Functions
      3. 10.3.3 OUTPUTXBAR Registers to Driverlib Functions
    4. 10.4 XBAR Registers
      1. 10.4.1 XBAR Base Address Table
      2. 10.4.2 INPUT_XBAR_REGS Registers
      3. 10.4.3 XBAR_REGS Registers
      4. 10.4.4 EPWM_XBAR_REGS Registers
      5. 10.4.5 CLB_XBAR_REGS Registers
      6. 10.4.6 OUTPUT_XBAR_REGS Registers
      7. 10.4.7 OUTPUT_XBAR_REGS Registers
  13. 11Direct Memory Access (DMA)
    1. 11.1 Introduction
      1. 11.1.1 Features
      2. 11.1.2 Block Diagram
    2. 11.2 Architecture
      1. 11.2.1 Peripheral Interrupt Event Trigger Sources
      2. 11.2.2 DMA Bus
    3. 11.3 Address Pointer and Transfer Control
    4. 11.4 Pipeline Timing and Throughput
    5. 11.5 CPU and CLA Arbitration
    6. 11.6 Channel Priority
      1. 11.6.1 Round-Robin Mode
      2. 11.6.2 Channel 1 High-Priority Mode
    7. 11.7 Overrun Detection Feature
    8. 11.8 Software
      1. 11.8.1 DMA Registers to Driverlib Functions
      2. 11.8.2 DMA Examples
        1. 11.8.2.1 DMA GSRAM Transfer (dma_ex1_gsram_transfer)
        2. 11.8.2.2 DMA GSRAM Transfer (dma_ex2_gsram_transfer)
    9. 11.9 DMA Registers
      1. 11.9.1 DMA Base Address Table
      2. 11.9.2 DMA_REGS Registers
      3. 11.9.3 DMA_CH_REGS Registers
  14. 12Embedded Real-time Analysis and Diagnostic (ERAD)
    1. 12.1 Introduction
      1. 12.1.1 ERAD Related Collateral
    2. 12.2 Enhanced Bus Comparator Unit
      1. 12.2.1 Enhanced Bus Comparator Unit Operations
      2. 12.2.2 Event Masking and Exporting
    3. 12.3 System Event Counter Unit
      1. 12.3.1 System Event Counter Modes
        1. 12.3.1.1 Counting Active Levels Versus Edges
        2. 12.3.1.2 Max Mode
        3. 12.3.1.3 Cumulative Mode
        4. 12.3.1.4 Input Signal Selection
      2. 12.3.2 Reset on Event
      3. 12.3.3 Operation Conditions
    4. 12.4 ERAD Ownership, Initialization and Reset
    5. 12.5 ERAD Programming Sequence
      1. 12.5.1 Hardware Breakpoint and Hardware Watch Point Programming Sequence
      2. 12.5.2 Timer and Counter Programming Sequence
    6. 12.6 Cyclic Redundancy Check Unit
      1. 12.6.1 CRC Unit Qualifier
      2. 12.6.2 CRC Unit Programming Sequence
    7. 12.7 Program Counter Trace
      1. 12.7.1 Functional Block Diagram
      2. 12.7.2 Trace Qualification Modes
        1. 12.7.2.1 Trace Qualifier Input Signals
      3. 12.7.3 Trace Memory
      4. 12.7.4 Trace Input Signal Conditioning
      5. 12.7.5 PC Trace Software Operation
      6. 12.7.6 Trace Operation in Debug Mode
    8. 12.8 Software
      1. 12.8.1 ERAD Registers to Driverlib Functions
      2. 12.8.2 ERAD Examples
        1. 12.8.2.1  ERAD Profiling Interrupts
        2. 12.8.2.2  ERAD Profile Function
        3. 12.8.2.3  ERAD Profile Function
        4. 12.8.2.4  ERAD HWBP Monitor Program Counter
        5. 12.8.2.5  ERAD HWBP Monitor Program Counter
        6. 12.8.2.6  ERAD Profile Function
        7. 12.8.2.7  ERAD HWBP Stack Overflow Detection
        8. 12.8.2.8  ERAD HWBP Stack Overflow Detection
        9. 12.8.2.9  ERAD Stack Overflow
        10. 12.8.2.10 ERAD Profile Interrupts CLA
        11. 12.8.2.11 ERAD Profiling Interrupts
        12. 12.8.2.12 ERAD Profiling Interrupts
        13. 12.8.2.13 ERAD MEMORY ACCESS RESTRICT
        14. 12.8.2.14 ERAD INTERRUPT ORDER
        15. 12.8.2.15 ERAD AND CLB
        16. 12.8.2.16 ERAD PWM PROTECTION
    9. 12.9 ERAD Registers
      1. 12.9.1 ERAD Base Address Table
      2. 12.9.2 ERAD_GLOBAL_REGS Registers
      3. 12.9.3 ERAD_HWBP_REGS Registers
      4. 12.9.4 ERAD_COUNTER_REGS Registers
      5. 12.9.5 ERAD_CRC_GLOBAL_REGS Registers
      6. 12.9.6 ERAD_CRC_REGS Registers
      7. 12.9.7 PCTRACE_REGS Registers
      8. 12.9.8 PCTRACE_BUFFER_REGS Registers
  15. 13Analog Subsystem
    1. 13.1 Introduction
      1. 13.1.1 Features
      2. 13.1.2 Block Diagram
    2. 13.2 Optimizing Power-Up Time
    3. 13.3 Digital Inputs on ADC Pins (AIOs)
    4. 13.4 Digital Inputs and Outputs on ADC Pins (AGPIOs)
    5. 13.5 Analog Pins and Internal Connections
    6. 13.6 Software
      1. 13.6.1 ASYSCTL Registers to Driverlib Functions
    7. 13.7 ASBSYS Registers
      1. 13.7.1 ASBSYS Base Address Table
      2. 13.7.2 ANALOG_SUBSYS_REGS Registers
  16. 14Analog-to-Digital Converter (ADC)
    1. 14.1  Introduction
      1. 14.1.1 ADC Related Collateral
      2. 14.1.2 Features
      3. 14.1.3 Block Diagram
    2. 14.2  ADC Configurability
      1. 14.2.1 Clock Configuration
      2. 14.2.2 Resolution
      3. 14.2.3 Voltage Reference
        1. 14.2.3.1 External Reference Mode
        2. 14.2.3.2 Internal Reference Mode
        3. 14.2.3.3 Ganged References
        4. 14.2.3.4 Selecting Reference Mode
      4. 14.2.4 Signal Mode
      5. 14.2.5 Expected Conversion Results
      6. 14.2.6 Interpreting Conversion Results
    3. 14.3  SOC Principle of Operation
      1. 14.3.1 SOC Configuration
      2. 14.3.2 Trigger Operation
        1. 14.3.2.1 Global Software Trigger
        2. 14.3.2.2 Trigger Repeaters
          1. 14.3.2.2.1 Oversampling Mode
          2. 14.3.2.2.2 Undersampling Mode
          3. 14.3.2.2.3 Trigger Phase Delay
          4. 14.3.2.2.4 Re-trigger Spread
          5. 14.3.2.2.5 Trigger Repeater Configuration
            1. 14.3.2.2.5.1 Register Shadow Updates
          6. 14.3.2.2.6 Re-Trigger Logic
          7. 14.3.2.2.7 Multi-Path Triggering Behavior
      3. 14.3.3 ADC Acquisition (Sample and Hold) Window
      4. 14.3.4 Sample Capacitor Reset
      5. 14.3.5 ADC Input Models
      6. 14.3.6 Channel Selection
        1. 14.3.6.1 External Channel Selection
          1. 14.3.6.1.1 External Channel Selection Timing
    4. 14.4  SOC Configuration Examples
      1. 14.4.1 Single Conversion from ePWM Trigger
      2. 14.4.2 Multiple Conversions from CPU Timer Trigger
      3. 14.4.3 Software Triggering of SOCs
    5. 14.5  ADC Conversion Priority
    6. 14.6  Burst Mode
      1. 14.6.1 Burst Mode Example
      2. 14.6.2 Burst Mode Priority Example
    7. 14.7  EOC and Interrupt Operation
      1. 14.7.1 Interrupt Overflow
      2. 14.7.2 Continue to Interrupt Mode
      3. 14.7.3 Early Interrupt Configuration Mode
    8. 14.8  Post-Processing Blocks
      1. 14.8.1 PPB Offset Correction
      2. 14.8.2 PPB Error Calculation
      3. 14.8.3 PPB Result Delta Calculation
      4. 14.8.4 PPB Limit Detection and Zero-Crossing Detection
        1. 14.8.4.1 PPB Digital Trip Filter
      5. 14.8.5 PPB Sample Delay Capture
      6. 14.8.6 PPB Oversampling
        1. 14.8.6.1 Accumulation, Average, Minimum, and Maximum Functions
        2. 14.8.6.2 Outlier Rejection
    9. 14.9  Power-Up Sequence
    10. 14.10 ADC Calibration
      1. 14.10.1 ADC Zero Offset Calibration
    11. 14.11 ADC Timings
      1. 14.11.1 ADC Timing Diagrams
      2. 14.11.2 Post-Processing Block Timings
    12. 14.12 Additional Information
      1. 14.12.1 Ensuring Synchronous Operation
        1. 14.12.1.1 Basic Synchronous Operation
        2. 14.12.1.2 Synchronous Operation with Multiple Trigger Sources
        3. 14.12.1.3 Synchronous Operation with Uneven SOC Numbers
        4. 14.12.1.4 Non-overlapping Conversions
      2. 14.12.2 Choosing an Acquisition Window Duration
      3. 14.12.3 Achieving Simultaneous Sampling
      4. 14.12.4 Result Register Mapping
      5. 14.12.5 Internal Temperature Sensor
      6. 14.12.6 Designing an External Reference Circuit
      7. 14.12.7 ADC-DAC Loopback Testing
      8. 14.12.8 Internal Test Mode
      9. 14.12.9 ADC Gain and Offset Calibration
    13. 14.13 Software
      1. 14.13.1 ADC Registers to Driverlib Functions
      2. 14.13.2 ADC Examples
        1. 14.13.2.1  ADC Software Triggering
        2. 14.13.2.2  ADC ePWM Triggering
        3. 14.13.2.3  ADC Temperature Sensor Conversion
        4. 14.13.2.4  ADC Synchronous SOC Software Force (adc_soc_software_sync)
        5. 14.13.2.5  ADC Continuous Triggering (adc_soc_continuous)
        6. 14.13.2.6  ADC Continuous Conversions Read by DMA (adc_soc_continuous_dma)
        7. 14.13.2.7  ADC PPB Offset (adc_ppb_offset)
        8. 14.13.2.8  ADC PPB Limits (adc_ppb_limits)
        9. 14.13.2.9  ADC PPB Delay Capture (adc_ppb_delay)
        10. 14.13.2.10 ADC ePWM Triggering Multiple SOC
        11. 14.13.2.11 ADC Burst Mode
        12. 14.13.2.12 ADC Burst Mode Oversampling
        13. 14.13.2.13 ADC SOC Oversampling
        14. 14.13.2.14 ADC PPB PWM trip (adc_ppb_pwm_trip)
    14. 14.14 ADC Registers
      1. 14.14.1 ADC Base Address Table
      2. 14.14.2 ADC_RESULT_REGS Registers
      3. 14.14.3 ADC_REGS Registers
  17. 15Buffered Digital-to-Analog Converter (DAC)
    1. 15.1 Introduction
      1. 15.1.1 DAC Related Collateral
      2. 15.1.2 Features
      3. 15.1.3 Block Diagram
    2. 15.2 Using the DAC
      1. 15.2.1 Initialization Sequence
      2. 15.2.2 DAC Offset Adjustment
      3. 15.2.3 EPWMSYNCPER Signal
    3. 15.3 Lock Registers
    4. 15.4 Software
      1. 15.4.1 DAC Registers to Driverlib Functions
      2. 15.4.2 DAC Examples
        1. 15.4.2.1 Buffered DAC Enable
        2. 15.4.2.2 Buffered DAC Random
        3. 15.4.2.3 Buffered DAC Sine (buffdac_sine)
    5. 15.5 DAC Registers
      1. 15.5.1 DAC Base Address Table
      2. 15.5.2 DAC_REGS Registers
  18. 16Comparator Subsystem (CMPSS)
    1. 16.1 Introduction
      1. 16.1.1 CMPSS Related Collateral
      2. 16.1.2 Features
      3. 16.1.3 Block Diagram
    2. 16.2 Comparator
    3. 16.3 Reference DAC
    4. 16.4 Ramp Generator
      1. 16.4.1 Ramp Generator Overview
      2. 16.4.2 Ramp Generator Behavior
      3. 16.4.3 Ramp Generator Behavior at Corner Cases
    5. 16.5 Digital Filter
      1. 16.5.1 Filter Initialization Sequence
    6. 16.6 Using the CMPSS
      1. 16.6.1 LATCHCLR, EPWMSYNCPER, and EPWMBLANK Signals
      2. 16.6.2 Synchronizer, Digital Filter, and Latch Delays
      3. 16.6.3 Calibrating the CMPSS
      4. 16.6.4 Enabling and Disabling the CMPSS Clock
    7. 16.7 CMPSS DAC Output
    8. 16.8 Software
      1. 16.8.1 CMPSS Registers to Driverlib Functions
      2. 16.8.2 CMPSS Examples
        1. 16.8.2.1 CMPSS Asynchronous Trip
        2. 16.8.2.2 CMPSS Digital Filter Configuration
    9. 16.9 CMPSS Registers
      1. 16.9.1 CMPSS Base Address Table
      2. 16.9.2 CMPSS_REGS Registers
  19. 17Programmable Gain Amplifier (PGA)
    1. 17.1  Programmable Gain Amplifier (PGA) Overview
      1. 17.1.1 Features
      2. 17.1.2 Block Diagram
    2. 17.2  Linear Output Range
    3. 17.3  Gain Values
    4. 17.4  Modes of Operation
      1. 17.4.1 Buffer Mode
      2. 17.4.2 Standalone Mode
      3. 17.4.3 Non-inverting Mode
      4. 17.4.4 Subtractor Mode
    5. 17.5  External Filtering
      1. 17.5.1 Low-Pass Filter Using Internal Filter Resistor and External Capacitor
      2. 17.5.2 Single Pole Low-Pass Filter Using Internal Gain Resistor and External Capacitor
    6. 17.6  Error Calibration
      1. 17.6.1 Offset Error
      2. 17.6.2 Gain Error
    7. 17.7  Chopping Feature
    8. 17.8  Enabling and Disabling the PGA Clock
    9. 17.9  Lock Register
    10. 17.10 Analog Front-End Integration
      1. 17.10.1 Buffered DAC
      2. 17.10.2 Analog-to-Digital Converter (ADC)
        1. 17.10.2.1 Unfiltered Acquisition Window
        2. 17.10.2.2 Filtered Acquisition Window
      3. 17.10.3 Comparator Subsystem (CMPSS)
      4. 17.10.4 PGA_NEG_SHARED Feature
      5. 17.10.5 Alternate Functions
    11. 17.11 Examples
      1. 17.11.1 Non-Inverting Amplifier Using Non-Inverting Mode
      2. 17.11.2 Buffer Mode
      3. 17.11.3 Low-Side Current Sensing
      4. 17.11.4 Bidirectional Current Sensing
    12. 17.12 Software
      1. 17.12.1 PGA Registers to Driverlib Functions
      2. 17.12.2 PGA Examples
        1. 17.12.2.1 PGA DAC-ADC External Loopback Example
    13. 17.13 PGA Registers
      1. 17.13.1 PGA Base Address Table
      2. 17.13.2 PGA_REGS Registers
  20. 18Enhanced Pulse Width Modulator (ePWM)
    1. 18.1  Introduction
      1. 18.1.1 EPWM Related Collateral
      2. 18.1.2 Submodule Overview
    2. 18.2  Configuring Device Pins
    3. 18.3  ePWM Modules Overview
    4. 18.4  Time-Base (TB) Submodule
      1. 18.4.1 Purpose of the Time-Base Submodule
      2. 18.4.2 Controlling and Monitoring the Time-Base Submodule
      3. 18.4.3 Calculating PWM Period and Frequency
        1. 18.4.3.1 Time-Base Period Shadow Register
        2. 18.4.3.2 Time-Base Clock Synchronization
        3. 18.4.3.3 Time-Base Counter Synchronization
        4. 18.4.3.4 ePWM SYNC Selection
      4. 18.4.4 Phase Locking the Time-Base Clocks of Multiple ePWM Modules
      5. 18.4.5 Simultaneous Writes to TBPRD and CMPx Registers Between ePWM Modules
      6. 18.4.6 Time-Base Counter Modes and Timing Waveforms
      7. 18.4.7 Global Load
        1. 18.4.7.1 Global Load Pulse Pre-Scalar
        2. 18.4.7.2 One-Shot Load Mode
        3. 18.4.7.3 One-Shot Sync Mode
    5. 18.5  Counter-Compare (CC) Submodule
      1. 18.5.1 Purpose of the Counter-Compare Submodule
      2. 18.5.2 Controlling and Monitoring the Counter-Compare Submodule
      3. 18.5.3 Operational Highlights for the Counter-Compare Submodule
      4. 18.5.4 Count Mode Timing Waveforms
    6. 18.6  Action-Qualifier (AQ) Submodule
      1. 18.6.1 Purpose of the Action-Qualifier Submodule
      2. 18.6.2 Action-Qualifier Submodule Control and Status Register Definitions
      3. 18.6.3 Action-Qualifier Event Priority
      4. 18.6.4 AQCTLA and AQCTLB Shadow Mode Operations
      5. 18.6.5 Configuration Requirements for Common Waveforms
    7. 18.7  Dead-Band Generator (DB) Submodule
      1. 18.7.1 Purpose of the Dead-Band Submodule
      2. 18.7.2 Dead-band Submodule Additional Operating Modes
      3. 18.7.3 Operational Highlights for the Dead-Band Submodule
    8. 18.8  PWM Chopper (PC) Submodule
      1. 18.8.1 Purpose of the PWM Chopper Submodule
      2. 18.8.2 Operational Highlights for the PWM Chopper Submodule
      3. 18.8.3 Waveforms
        1. 18.8.3.1 One-Shot Pulse
        2. 18.8.3.2 Duty Cycle Control
    9. 18.9  Trip-Zone (TZ) Submodule
      1. 18.9.1 Purpose of the Trip-Zone Submodule
      2. 18.9.2 Operational Highlights for the Trip-Zone Submodule
        1. 18.9.2.1 Trip-Zone Configurations
      3. 18.9.3 Generating Trip Event Interrupts
    10. 18.10 Event-Trigger (ET) Submodule
      1. 18.10.1 Operational Overview of the ePWM Event-Trigger Submodule
    11. 18.11 Digital Compare (DC) Submodule
      1. 18.11.1 Purpose of the Digital Compare Submodule
      2. 18.11.2 Enhanced Trip Action Using CMPSS
      3. 18.11.3 Using CMPSS to Trip the ePWM on a Cycle-by-Cycle Basis
      4. 18.11.4 Operation Highlights of the Digital Compare Submodule
        1. 18.11.4.1 Digital Compare Events
        2. 18.11.4.2 Event Filtering
        3. 18.11.4.3 Valley Switching
    12. 18.12 ePWM Crossbar (X-BAR)
    13. 18.13 Applications to Power Topologies
      1. 18.13.1  Overview of Multiple Modules
      2. 18.13.2  Key Configuration Capabilities
      3. 18.13.3  Controlling Multiple Buck Converters With Independent Frequencies
      4. 18.13.4  Controlling Multiple Buck Converters With Same Frequencies
      5. 18.13.5  Controlling Multiple Half H-Bridge (HHB) Converters
      6. 18.13.6  Controlling Dual 3-Phase Inverters for Motors (ACI and PMSM)
      7. 18.13.7  Practical Applications Using Phase Control Between PWM Modules
      8. 18.13.8  Controlling a 3-Phase Interleaved DC/DC Converter
      9. 18.13.9  Controlling Zero Voltage Switched Full Bridge (ZVSFB) Converter
      10. 18.13.10 Controlling a Peak Current Mode Controlled Buck Module
      11. 18.13.11 Controlling H-Bridge LLC Resonant Converter
    14. 18.14 Register Lock Protection
    15. 18.15 High-Resolution Pulse Width Modulator (HRPWM)
      1. 18.15.1 Operational Description of HRPWM
        1. 18.15.1.1 Controlling the HRPWM Capabilities
        2. 18.15.1.2 HRPWM Source Clock
        3. 18.15.1.3 Configuring the HRPWM
        4. 18.15.1.4 Configuring High-Resolution in Deadband Rising-Edge and Falling-Edge Delay
        5. 18.15.1.5 Principle of Operation
          1. 18.15.1.5.1 Edge Positioning
          2. 18.15.1.5.2 Scaling Considerations
          3. 18.15.1.5.3 Duty Cycle Range Limitation
          4. 18.15.1.5.4 High-Resolution Period
            1. 18.15.1.5.4.1 High-Resolution Period Configuration
        6. 18.15.1.6 Deadband High-Resolution Operation
        7. 18.15.1.7 Scale Factor Optimizing Software (SFO)
        8. 18.15.1.8 HRPWM Examples Using Optimized Assembly Code
          1. 18.15.1.8.1 #Defines for HRPWM Header Files
          2. 18.15.1.8.2 Implementing a Simple Buck Converter
            1. 18.15.1.8.2.1 HRPWM Buck Converter Initialization Code
            2. 18.15.1.8.2.2 HRPWM Buck Converter Run-Time Code
          3. 18.15.1.8.3 Implementing a DAC Function Using an R+C Reconstruction Filter
            1. 18.15.1.8.3.1 PWM DAC Function Initialization Code
            2. 18.15.1.8.3.2 PWM DAC Function Run-Time Code
      2. 18.15.2 SFO Library Software - SFO_TI_Build_V8.lib
        1. 18.15.2.1 Scale Factor Optimizer Function - int SFO()
        2. 18.15.2.2 Software Usage
          1. 18.15.2.2.1 A Sample of How to Add "Include" Files
          2.        912
          3. 18.15.2.2.2 Declaring an Element
          4.        914
          5. 18.15.2.2.3 Initializing With a Scale Factor Value
          6.        916
          7. 18.15.2.2.4 SFO Function Calls
    16. 18.16 Software
      1. 18.16.1 EPWM Registers to Driverlib Functions
      2. 18.16.2 EPWMXBAR Registers to Driverlib Functions
      3. 18.16.3 HRPWM Registers to Driverlib Functions
      4. 18.16.4 EPWM Examples
        1. 18.16.4.1  ePWM Trip Zone
        2. 18.16.4.2  ePWM Up Down Count Action Qualifier
        3. 18.16.4.3  ePWM Synchronization
        4. 18.16.4.4  ePWM Digital Compare
        5. 18.16.4.5  ePWM Digital Compare Event Filter Blanking Window
        6. 18.16.4.6  ePWM Valley Switching
        7. 18.16.4.7  ePWM Digital Compare Edge Filter
        8. 18.16.4.8  ePWM Deadband
        9. 18.16.4.9  ePWM DMA
        10. 18.16.4.10 ePWM Chopper
        11. 18.16.4.11 EPWM Configure Signal
        12. 18.16.4.12 Realization of Monoshot mode
        13. 18.16.4.13 EPWM Action Qualifier (epwm_up_aq)
      5. 18.16.5 HRPWM Examples
        1. 18.16.5.1 HRPWM Duty Control with SFO
        2. 18.16.5.2 HRPWM Slider
        3. 18.16.5.3 HRPWM Period Control
        4. 18.16.5.4 HRPWM Duty Control with UPDOWN Mode
        5. 18.16.5.5 HRPWM Slider Test
        6. 18.16.5.6 HRPWM Duty Up Count
        7. 18.16.5.7 HRPWM Period Up-Down Count
    17. 18.17 EPWM Registers
      1. 18.17.1 EPWM Base Address Table
      2. 18.17.2 EPWM_REGS Registers
  21. 19Enhanced Capture (eCAP)
    1. 19.1 Introduction
      1. 19.1.1 Features
      2. 19.1.2 ECAP Related Collateral
    2. 19.2 Description
    3. 19.3 Configuring Device Pins for the eCAP
    4. 19.4 Capture and APWM Operating Mode
    5. 19.5 Capture Mode Description
      1. 19.5.1  Event Prescaler
      2. 19.5.2  Edge Polarity Select and Qualifier
      3. 19.5.3  Continuous/One-Shot Control
      4. 19.5.4  32-Bit Counter and Phase Control
      5. 19.5.5  CAP1-CAP4 Registers
      6. 19.5.6  eCAP Synchronization
        1. 19.5.6.1 Example 1 - Using SWSYNC with ECAP Module
      7. 19.5.7  Interrupt Control
      8. 19.5.8  DMA Interrupt
      9. 19.5.9  Shadow Load and Lockout Control
      10. 19.5.10 APWM Mode Operation
    6. 19.6 Application of the eCAP Module
      1. 19.6.1 Example 1 - Absolute Time-Stamp Operation Rising-Edge Trigger
      2. 19.6.2 Example 2 - Absolute Time-Stamp Operation Rising- and Falling-Edge Trigger
      3. 19.6.3 Example 3 - Time Difference (Delta) Operation Rising-Edge Trigger
      4. 19.6.4 Example 4 - Time Difference (Delta) Operation Rising- and Falling-Edge Trigger
    7. 19.7 Application of the APWM Mode
      1. 19.7.1 Example 1 - Simple PWM Generation (Independent Channels)
    8. 19.8 Software
      1. 19.8.1 ECAP Registers to Driverlib Functions
      2. 19.8.2 ECAP Examples
        1. 19.8.2.1 eCAP APWM Example
        2. 19.8.2.2 eCAP Capture PWM Example
        3. 19.8.2.3 eCAP APWM Phase-shift Example
    9. 19.9 ECAP Registers
      1. 19.9.1 ECAP Base Address Table
      2. 19.9.2 ECAP_REGS Registers
  22. 20Enhanced Quadrature Encoder Pulse (eQEP)
    1. 20.1  Introduction
      1. 20.1.1 EQEP Related Collateral
    2. 20.2  Configuring Device Pins
    3. 20.3  Description
      1. 20.3.1 EQEP Inputs
      2. 20.3.2 Functional Description
      3. 20.3.3 eQEP Memory Map
    4. 20.4  Quadrature Decoder Unit (QDU)
      1. 20.4.1 Position Counter Input Modes
        1. 20.4.1.1 Quadrature Count Mode
        2. 20.4.1.2 Direction-Count Mode
        3. 20.4.1.3 Up-Count Mode
        4. 20.4.1.4 Down-Count Mode
      2. 20.4.2 eQEP Input Polarity Selection
      3. 20.4.3 Position-Compare Sync Output
    5. 20.5  Position Counter and Control Unit (PCCU)
      1. 20.5.1 Position Counter Operating Modes
        1. 20.5.1.1 Position Counter Reset on Index Event (QEPCTL[PCRM]=00)
        2. 20.5.1.2 Position Counter Reset on Maximum Position (QEPCTL[PCRM]=01)
        3. 20.5.1.3 Position Counter Reset on the First Index Event (QEPCTL[PCRM] = 10)
        4. 20.5.1.4 Position Counter Reset on Unit Time-out Event (QEPCTL[PCRM] = 11)
      2. 20.5.2 Position Counter Latch
        1. 20.5.2.1 Index Event Latch
        2. 20.5.2.2 Strobe Event Latch
      3. 20.5.3 Position Counter Initialization
      4. 20.5.4 eQEP Position-compare Unit
    6. 20.6  eQEP Edge Capture Unit
    7. 20.7  eQEP Watchdog
    8. 20.8  eQEP Unit Timer Base
    9. 20.9  QMA Module
      1. 20.9.1 Modes of Operation
        1. 20.9.1.1 QMA Mode-1 (QMACTRL[MODE]=1)
        2. 20.9.1.2 QMA Mode-2 (QMACTRL[MODE]=2)
      2. 20.9.2 Interrupt and Error Generation
    10. 20.10 eQEP Interrupt Structure
    11. 20.11 Software
      1. 20.11.1 EQEP Registers to Driverlib Functions
      2. 20.11.2 EQEP Examples
        1. 20.11.2.1 Frequency Measurement Using eQEP
        2. 20.11.2.2 Position and Speed Measurement Using eQEP
        3. 20.11.2.3 Frequency Measurement Using eQEP via unit timeout interrupt
        4. 20.11.2.4 Motor speed and direction measurement using eQEP via unit timeout interrupt
    12. 20.12 EQEP Registers
      1. 20.12.1 EQEP Base Address Table
      2. 20.12.2 EQEP_REGS Registers
  23. 21Serial Peripheral Interface (SPI)
    1. 21.1 Introduction
      1. 21.1.1 Features
      2. 21.1.2 SPI Related Collateral
      3. 21.1.3 Block Diagram
    2. 21.2 System-Level Integration
      1. 21.2.1 SPI Module Signals
      2. 21.2.2 Configuring Device Pins
        1. 21.2.2.1 GPIOs Required for High-Speed Mode
      3. 21.2.3 SPI Interrupts
      4. 21.2.4 DMA Support
    3. 21.3 SPI Operation
      1. 21.3.1  Introduction to Operation
      2. 21.3.2  Controller Mode
      3. 21.3.3  Peripheral Mode
      4. 21.3.4  Data Format
        1. 21.3.4.1 Transmission of Bit from SPIRXBUF
      5. 21.3.5  Baud Rate Selection
        1. 21.3.5.1 Baud Rate Determination
        2. 21.3.5.2 Baud Rate Calculation in Non-High Speed Mode (HS_MODE = 0)
      6. 21.3.6  SPI Clocking Schemes
      7. 21.3.7  SPI FIFO Description
      8. 21.3.8  SPI DMA Transfers
        1. 21.3.8.1 Transmitting Data Using SPI with DMA
        2. 21.3.8.2 Receiving Data Using SPI with DMA
      9. 21.3.9  SPI High-Speed Mode
      10. 21.3.10 SPI 3-Wire Mode Description
    4. 21.4 Programming Procedure
      1. 21.4.1 Initialization Upon Reset
      2. 21.4.2 Configuring the SPI
      3. 21.4.3 Configuring the SPI for High-Speed Mode
      4. 21.4.4 Data Transfer Example
      5. 21.4.5 SPI 3-Wire Mode Code Examples
        1. 21.4.5.1 3-Wire Controller Mode Transmit
        2.       1062
          1. 21.4.5.2.1 3-Wire Controller Mode Receive
        3.       1064
          1. 21.4.5.2.1 3-Wire Peripheral Mode Transmit
        4.       1066
          1. 21.4.5.2.1 3-Wire Peripheral Mode Receive
      6. 21.4.6 SPI STEINV Bit in Digital Audio Transfers
    5. 21.5 Software
      1. 21.5.1 SPI Registers to Driverlib Functions
      2. 21.5.2 SPI Examples
        1. 21.5.2.1 SPI Digital Loopback
        2. 21.5.2.2 SPI Digital Loopback with FIFO Interrupts
        3. 21.5.2.3 SPI Digital External Loopback without FIFO Interrupts
        4. 21.5.2.4 SPI Digital External Loopback with FIFO Interrupts
        5. 21.5.2.5 SPI Digital Loopback with DMA
        6. 21.5.2.6 SPI EEPROM
        7. 21.5.2.7 SPI DMA EEPROM
    6. 21.6 SPI Registers
      1. 21.6.1 SPI Base Address Table
      2. 21.6.2 SPI_REGS Registers
  24. 22Serial Communications Interface (SCI)
    1. 22.1  Introduction
      1. 22.1.1 Features
      2. 22.1.2 SCI Related Collateral
      3. 22.1.3 Block Diagram
    2. 22.2  Architecture
    3. 22.3  SCI Module Signal Summary
    4. 22.4  Configuring Device Pins
    5. 22.5  Multiprocessor and Asynchronous Communication Modes
    6. 22.6  SCI Programmable Data Format
    7. 22.7  SCI Multiprocessor Communication
      1. 22.7.1 Recognizing the Address Byte
      2. 22.7.2 Controlling the SCI TX and RX Features
      3. 22.7.3 Receipt Sequence
    8. 22.8  Idle-Line Multiprocessor Mode
      1. 22.8.1 Idle-Line Mode Steps
      2. 22.8.2 Block Start Signal
      3. 22.8.3 Wake-Up Temporary (WUT) Flag
        1. 22.8.3.1 Sending a Block Start Signal
      4. 22.8.4 Receiver Operation
    9. 22.9  Address-Bit Multiprocessor Mode
      1. 22.9.1 Sending an Address
    10. 22.10 SCI Communication Format
      1. 22.10.1 Receiver Signals in Communication Modes
      2. 22.10.2 Transmitter Signals in Communication Modes
    11. 22.11 SCI Port Interrupts
      1. 22.11.1 Break Detect
    12. 22.12 SCI Baud Rate Calculations
    13. 22.13 SCI Enhanced Features
      1. 22.13.1 SCI FIFO Description
      2. 22.13.2 SCI Auto-Baud
      3. 22.13.3 Autobaud-Detect Sequence
    14. 22.14 Software
      1. 22.14.1 SCI Registers to Driverlib Functions
      2. 22.14.2 SCI Examples
        1. 22.14.2.1 Tune Baud Rate via UART Example
        2. 22.14.2.2 SCI FIFO Digital Loop Back
        3. 22.14.2.3 SCI Digital Loop Back with Interrupts
        4. 22.14.2.4 SCI Echoback
        5. 22.14.2.5 stdout redirect example
    15. 22.15 SCI Registers
      1. 22.15.1 SCI Base Address Table
      2. 22.15.2 SCI_REGS Registers
  25. 23Universal Serial Bus (USB) Controller
    1. 23.1 Introduction
      1. 23.1.1 Features
      2. 23.1.2 USB Related Collateral
      3. 23.1.3 Block Diagram
        1. 23.1.3.1 Signal Description
        2. 23.1.3.2 VBus Recommendations
    2. 23.2 Functional Description
      1. 23.2.1 Operation as a Device
        1. 23.2.1.1 Control and Configurable Endpoints
          1. 23.2.1.1.1 IN Transactions as a Device
          2. 23.2.1.1.2 Out Transactions as a Device
          3. 23.2.1.1.3 Scheduling
          4. 23.2.1.1.4 Additional Actions
          5. 23.2.1.1.5 Device Mode Suspend
          6. 23.2.1.1.6 Start of Frame
          7. 23.2.1.1.7 USB Reset
          8. 23.2.1.1.8 Connect/Disconnect
      2. 23.2.2 Operation as a Host
        1. 23.2.2.1 Endpoint Registers
        2. 23.2.2.2 IN Transactions as a Host
        3. 23.2.2.3 OUT Transactions as a Host
        4. 23.2.2.4 Transaction Scheduling
        5. 23.2.2.5 USB Hubs
        6. 23.2.2.6 Babble
        7. 23.2.2.7 Host SUSPEND
        8. 23.2.2.8 USB RESET
        9. 23.2.2.9 Connect/Disconnect
      3. 23.2.3 DMA Operation
      4. 23.2.4 Address/Data Bus Bridge
    3. 23.3 Initialization and Configuration
      1. 23.3.1 Pin Configuration
      2. 23.3.2 Endpoint Configuration
    4. 23.4 USB Global Interrupts
    5. 23.5 Software
      1. 23.5.1 USB Examples
        1. 23.5.1.1  USB CDC serial example
        2. 23.5.1.2  USB HID Mouse Device
        3. 23.5.1.3  USB Device Keyboard
        4. 23.5.1.4  USB Generic Bulk Device
        5. 23.5.1.5  USB HID Mouse Host
        6. 23.5.1.6  USB HID Keyboard Host
        7. 23.5.1.7  USB Mass Storage Class Host
        8. 23.5.1.8  USB Dual Detect
        9. 23.5.1.9  USB Throughput Bulk Device Example (usb_ex9_throughput_dev_bulk)
        10. 23.5.1.10 USB HUB Host example
    6. 23.6 USB Registers
      1. 23.6.1 USB Base Address Table
      2. 23.6.2 USB_REGS Registers
  26. 24Fast Serial Interface (FSI)
    1. 24.1 Introduction
      1. 24.1.1 FSI Related Collateral
      2. 24.1.2 FSI Features
    2. 24.2 System-level Integration
      1. 24.2.1 CPU Interface
      2. 24.2.2 Signal Description
        1. 24.2.2.1 Configuring Device Pins
      3. 24.2.3 FSI Interrupts
        1. 24.2.3.1 Transmitter Interrupts
        2. 24.2.3.2 Receiver Interrupts
        3. 24.2.3.3 Configuring Interrupts
        4. 24.2.3.4 Handling Interrupts
      4. 24.2.4 CLA Task Triggering
      5. 24.2.5 DMA Interface
      6. 24.2.6 External Frame Trigger Mux
    3. 24.3 FSI Functional Description
      1. 24.3.1  Introduction to Operation
      2. 24.3.2  FSI Transmitter Module
        1. 24.3.2.1 Initialization
        2. 24.3.2.2 FSI_TX Clocking
        3. 24.3.2.3 Transmitting Frames
          1. 24.3.2.3.1 Software Triggered Frames
          2. 24.3.2.3.2 Externally Triggered Frames
          3. 24.3.2.3.3 Ping Frame Generation
            1. 24.3.2.3.3.1 Automatic Ping Frames
            2. 24.3.2.3.3.2 Software Triggered Ping Frame
            3. 24.3.2.3.3.3 Externally Triggered Ping Frame
          4. 24.3.2.3.4 Transmitting Frames with DMA
        4. 24.3.2.4 Transmit Buffer Management
        5. 24.3.2.5 CRC Submodule
        6. 24.3.2.6 Conditions in Which the Transmitter Must Undergo a Soft Reset
        7. 24.3.2.7 Reset
      3. 24.3.3  FSI Receiver Module
        1. 24.3.3.1  Initialization
        2. 24.3.3.2  FSI_RX Clocking
        3. 24.3.3.3  Receiving Frames
          1. 24.3.3.3.1 Receiving Frames with DMA
        4. 24.3.3.4  Ping Frame Watchdog
        5. 24.3.3.5  Frame Watchdog
        6. 24.3.3.6  Delay Line Control
        7. 24.3.3.7  Buffer Management
        8. 24.3.3.8  CRC Submodule
        9. 24.3.3.9  Using the Zero Bits of the Receiver Tag Registers
        10. 24.3.3.10 Conditions in Which the Receiver Must Undergo a Soft Reset
        11. 24.3.3.11 FSI_RX Reset
      4. 24.3.4  Frame Format
        1. 24.3.4.1 FSI Frame Phases
        2. 24.3.4.2 Frame Types
          1. 24.3.4.2.1 Ping Frames
          2. 24.3.4.2.2 Error Frames
          3. 24.3.4.2.3 Data Frames
        3. 24.3.4.3 Multi-Lane Transmission
      5. 24.3.5  Flush Sequence
      6. 24.3.6  Internal Loopback
      7. 24.3.7  CRC Generation
      8. 24.3.8  ECC Module
      9. 24.3.9  Tag Matching
      10. 24.3.10 User Data Filtering (UDATA Matching)
      11. 24.3.11 TDM Configurations
      12. 24.3.12 FSI Trigger Generation
      13. 24.3.13 FSI-SPI Compatibility Mode
        1. 24.3.13.1 Available SPI Modes
          1. 24.3.13.1.1 FSITX as SPI Controller, Transmit Only
            1. 24.3.13.1.1.1 Initialization
            2. 24.3.13.1.1.2 Operation
          2. 24.3.13.1.2 FSIRX as SPI Peripheral, Receive Only
            1. 24.3.13.1.2.1 Initialization
            2. 24.3.13.1.2.2 Operation
          3. 24.3.13.1.3 FSITX and FSIRX Emulating a Full Duplex SPI Controller
            1. 24.3.13.1.3.1 Initialization
            2. 24.3.13.1.3.2 Operation
    4. 24.4 FSI Programing Guide
      1. 24.4.1 Establishing the Communication Link
        1. 24.4.1.1 Establishing the Communication Link from the Main Device
        2. 24.4.1.2 Establishing the Communication Link from the Remote Device
      2. 24.4.2 Register Protection
      3. 24.4.3 Emulation Mode
    5. 24.5 Software
      1. 24.5.1 FSI Registers to Driverlib Functions
      2. 24.5.2 FSI Examples
        1. 24.5.2.1 FSI Loopback:CPU Control
        2. 24.5.2.2 FSI DMA frame transfers:DMA Control
        3. 24.5.2.3 FSI data transfer by external trigger
        4. 24.5.2.4 FSI data transfers upon CPU Timer event
        5. 24.5.2.5 FSI and SPI communication(fsi_ex6_spi_main_tx)
        6. 24.5.2.6 FSI and SPI communication(fsi_ex7_spi_remote_rx)
        7. 24.5.2.7 FSI P2Point Connection:Rx Side
        8. 24.5.2.8 FSI P2Point Connection:Tx Side
    6. 24.6 FSI Registers
      1. 24.6.1 FSI Base Address Table
      2. 24.6.2 FSI_TX_REGS Registers
      3. 24.6.3 FSI_RX_REGS Registers
  27. 25Inter-Integrated Circuit Module (I2C)
    1. 25.1 Introduction
      1. 25.1.1 I2C Related Collateral
      2. 25.1.2 Features
      3. 25.1.3 Features Not Supported
      4. 25.1.4 Functional Overview
      5. 25.1.5 Clock Generation
      6. 25.1.6 I2C Clock Divider Registers (I2CCLKL and I2CCLKH)
        1. 25.1.6.1 Formula for the Controller Clock Period
    2. 25.2 Configuring Device Pins
    3. 25.3 I2C Module Operational Details
      1. 25.3.1  Input and Output Voltage Levels
      2. 25.3.2  Selecting Pullup Resistors
      3. 25.3.3  Data Validity
      4. 25.3.4  Operating Modes
      5. 25.3.5  I2C Module START and STOP Conditions
      6. 25.3.6  Non-repeat Mode versus Repeat Mode
      7. 25.3.7  Serial Data Formats
        1. 25.3.7.1 7-Bit Addressing Format
        2. 25.3.7.2 10-Bit Addressing Format
        3. 25.3.7.3 Free Data Format
        4. 25.3.7.4 Using a Repeated START Condition
      8. 25.3.8  Clock Synchronization
      9. 25.3.9  Clock Stretching
      10. 25.3.10 Arbitration
      11. 25.3.11 Digital Loopback Mode
      12. 25.3.12 NACK Bit Generation
    4. 25.4 Interrupt Requests Generated by the I2C Module
      1. 25.4.1 Basic I2C Interrupt Requests
      2. 25.4.2 I2C FIFO Interrupts
    5. 25.5 Resetting or Disabling the I2C Module
    6. 25.6 Software
      1. 25.6.1 I2C Registers to Driverlib Functions
      2. 25.6.2 I2C Examples
        1. 25.6.2.1  C28x-I2C Library source file for FIFO interrupts
        2. 25.6.2.2  C28x-I2C Library source file for FIFO using polling
        3. 25.6.2.3  C28x-I2C Library source file for FIFO interrupts
        4. 25.6.2.4  I2C Digital Loopback with FIFO Interrupts
        5. 25.6.2.5  I2C EEPROM
        6. 25.6.2.6  I2C Digital External Loopback with FIFO Interrupts
        7. 25.6.2.7  I2C EEPROM
        8. 25.6.2.8  I2C controller target communication using FIFO interrupts
        9. 25.6.2.9  I2C EEPROM
        10. 25.6.2.10 I2C Extended Clock Stretching Target RX
        11. 25.6.2.11 I2C Extended Clock Stretching Controller TX
    7. 25.7 I2C Registers
      1. 25.7.1 I2C Base Address Table
      2. 25.7.2 I2C_REGS Registers
  28. 26Power Management Bus Module (PMBus)
    1. 26.1 Introduction
      1. 26.1.1 PMBUS Related Collateral
      2. 26.1.2 Features
      3. 26.1.3 Block Diagram
    2. 26.2 Configuring Device Pins
    3. 26.3 Target Mode Operation
      1. 26.3.1 Configuration
      2. 26.3.2 Message Handling
        1. 26.3.2.1  Quick Command
        2. 26.3.2.2  Send Byte
        3. 26.3.2.3  Receive Byte
        4. 26.3.2.4  Write Byte and Write Word
        5. 26.3.2.5  Read Byte and Read Word
        6. 26.3.2.6  Process Call
        7. 26.3.2.7  Block Write
        8. 26.3.2.8  Block Read
        9. 26.3.2.9  Block Write-Block Read Process Call
        10. 26.3.2.10 Alert Response
        11. 26.3.2.11 Extended Command
        12. 26.3.2.12 Group Command
    4. 26.4 Controller Mode Operation
      1. 26.4.1 Configuration
      2. 26.4.2 Message Handling
        1. 26.4.2.1  Quick Command
        2. 26.4.2.2  Send Byte
        3. 26.4.2.3  Receive Byte
        4. 26.4.2.4  Write Byte and Write Word
        5. 26.4.2.5  Read Byte and Read Word
        6. 26.4.2.6  Process Call
        7. 26.4.2.7  Block Write
        8. 26.4.2.8  Block Read
        9. 26.4.2.9  Block Write-Block Read Process Call
        10. 26.4.2.10 Alert Response
        11. 26.4.2.11 Extended Command
        12. 26.4.2.12 Group Command
    5. 26.5 Software
      1. 26.5.1 PMBUS Registers to Driverlib Functions
    6. 26.6 PMBUS Registers
      1. 26.6.1 PMBUS Base Address Table
      2. 26.6.2 PMBUS_REGS Registers
  29. 27Modular Controller Area Network (MCAN)
    1. 27.1 MCAN Introduction
      1. 27.1.1 MCAN Related Collateral
      2. 27.1.2 MCAN Features
    2. 27.2 MCAN Environment
    3. 27.3 CAN Network Basics
    4. 27.4 MCAN Integration
    5. 27.5 MCAN Functional Description
      1. 27.5.1  Module Clocking Requirements
      2. 27.5.2  Interrupt Requests
      3. 27.5.3  Operating Modes
        1. 27.5.3.1 Software Initialization
        2. 27.5.3.2 Normal Operation
        3. 27.5.3.3 CAN FD Operation
      4. 27.5.4  Transmitter Delay Compensation
        1. 27.5.4.1 Description
        2. 27.5.4.2 Transmitter Delay Compensation Measurement
      5. 27.5.5  Restricted Operation Mode
      6. 27.5.6  Bus Monitoring Mode
      7. 27.5.7  Disabled Automatic Retransmission (DAR) Mode
        1. 27.5.7.1 Frame Transmission in DAR Mode
      8. 27.5.8  Clock Stop Mode
        1. 27.5.8.1 Suspend Mode
        2. 27.5.8.2 Wakeup Request
      9. 27.5.9  Test Modes
        1. 27.5.9.1 External Loop Back Mode
        2. 27.5.9.2 Internal Loop Back Mode
      10. 27.5.10 Timestamp Generation
        1. 27.5.10.1 External Timestamp Counter
      11. 27.5.11 Timeout Counter
      12. 27.5.12 Safety
        1. 27.5.12.1 ECC Wrapper
        2. 27.5.12.2 ECC Aggregator
          1. 27.5.12.2.1 ECC Aggregator Overview
          2. 27.5.12.2.2 ECC Aggregator Registers
        3. 27.5.12.3 Reads to ECC Control and Status Registers
        4. 27.5.12.4 ECC Interrupts
      13. 27.5.13 Rx Handling
        1. 27.5.13.1 Acceptance Filtering
          1. 27.5.13.1.1 Range Filter
          2. 27.5.13.1.2 Filter for Specific IDs
          3. 27.5.13.1.3 Classic Bit Mask Filter
          4. 27.5.13.1.4 Standard Message ID Filtering
          5. 27.5.13.1.5 Extended Message ID Filtering
        2. 27.5.13.2 Rx FIFOs
          1. 27.5.13.2.1 Rx FIFO Blocking Mode
          2. 27.5.13.2.2 Rx FIFO Overwrite Mode
        3. 27.5.13.3 Dedicated Rx Buffers
          1. 27.5.13.3.1 Rx Buffer Handling
      14. 27.5.14 Tx Handling
        1. 27.5.14.1 Transmit Pause
        2. 27.5.14.2 Dedicated Tx Buffers
        3. 27.5.14.3 Tx FIFO
        4. 27.5.14.4 Tx Queue
        5. 27.5.14.5 Mixed Dedicated Tx Buffers/Tx FIFO
        6. 27.5.14.6 Mixed Dedicated Tx Buffers/Tx Queue
        7. 27.5.14.7 Transmit Cancellation
        8. 27.5.14.8 Tx Event Handling
      15. 27.5.15 FIFO Acknowledge Handling
      16. 27.5.16 Message RAM
        1. 27.5.16.1 Message RAM Configuration
        2. 27.5.16.2 Rx Buffer and FIFO Element
        3. 27.5.16.3 Tx Buffer Element
        4. 27.5.16.4 Tx Event FIFO Element
        5. 27.5.16.5 Standard Message ID Filter Element
        6. 27.5.16.6 Extended Message ID Filter Element
    6. 27.6 Software
      1. 27.6.1 MCAN Registers to Driverlib Functions
      2. 27.6.2 MCAN Examples
        1. 27.6.2.1  MCAN Internal Loopback with Interrupt
        2. 27.6.2.2  MCAN Loopback with Interrupts Example Using SYSCONFIG Tool
        3. 27.6.2.3  MCAN receive using Rx Buffer
        4. 27.6.2.4  MCAN External Reception (with mask filter) into RX-FIFO1
        5. 27.6.2.5  MCAN Classic frames transmission using Tx Buffer
        6. 27.6.2.6  MCAN External Reception (with RANGE filter) into RX-FIFO1
        7. 27.6.2.7  MCAN External Transmit using Tx Buffer
        8. 27.6.2.8  MCAN receive using Rx Buffer
        9. 27.6.2.9  MCAN Internal Loopback with Interrupt
        10. 27.6.2.10 MCAN External Transmit using Tx Buffer
    7. 27.7 MCAN Registers
      1. 27.7.1 MCAN Base Address Table
      2. 27.7.2 MCANSS_REGS Registers
      3. 27.7.3 MCAN_REGS Registers
      4. 27.7.4 MCAN_ERROR_REGS Registers
  30. 28Local Interconnect Network (LIN)
    1. 28.1 Introduction
      1. 28.1.1 SCI Features
      2. 28.1.2 LIN Features
      3. 28.1.3 LIN Related Collateral
      4. 28.1.4 Block Diagram
    2. 28.2 Serial Communications Interface Module
      1. 28.2.1 SCI Communication Formats
        1. 28.2.1.1 SCI Frame Formats
        2. 28.2.1.2 SCI Asynchronous Timing Mode
        3. 28.2.1.3 SCI Baud Rate
          1. 28.2.1.3.1 Superfractional Divider, SCI Asynchronous Mode
        4. 28.2.1.4 SCI Multiprocessor Communication Modes
          1. 28.2.1.4.1 Idle-Line Multiprocessor Modes
          2. 28.2.1.4.2 Address-Bit Multiprocessor Mode
        5. 28.2.1.5 SCI Multibuffered Mode
      2. 28.2.2 SCI Interrupts
        1. 28.2.2.1 Transmit Interrupt
        2. 28.2.2.2 Receive Interrupt
        3. 28.2.2.3 WakeUp Interrupt
        4. 28.2.2.4 Error Interrupts
      3. 28.2.3 SCI DMA Interface
        1. 28.2.3.1 Receive DMA Requests
        2. 28.2.3.2 Transmit DMA Requests
      4. 28.2.4 SCI Configurations
        1. 28.2.4.1 Receiving Data
          1. 28.2.4.1.1 Receiving Data in Single-Buffer Mode
          2. 28.2.4.1.2 Receiving Data in Multibuffer Mode
        2. 28.2.4.2 Transmitting Data
          1. 28.2.4.2.1 Transmitting Data in Single-Buffer Mode
          2. 28.2.4.2.2 Transmitting Data in Multibuffer Mode
      5. 28.2.5 SCI Low-Power Mode
        1. 28.2.5.1 Sleep Mode for Multiprocessor Communication
    3. 28.3 Local Interconnect Network Module
      1. 28.3.1 LIN Communication Formats
        1. 28.3.1.1  LIN Standards
        2. 28.3.1.2  Message Frame
          1. 28.3.1.2.1 Message Header
          2. 28.3.1.2.2 Response
        3. 28.3.1.3  Synchronizer
        4. 28.3.1.4  Baud Rate
          1. 28.3.1.4.1 Fractional Divider
          2. 28.3.1.4.2 Superfractional Divider
            1. 28.3.1.4.2.1 Superfractional Divider In LIN Mode
        5. 28.3.1.5  Header Generation
          1. 28.3.1.5.1 Event Triggered Frame Handling
          2. 28.3.1.5.2 Header Reception and Adaptive Baud Rate
        6. 28.3.1.6  Extended Frames Handling
        7. 28.3.1.7  Timeout Control
          1. 28.3.1.7.1 No-Response Error (NRE)
          2. 28.3.1.7.2 Bus Idle Detection
          3. 28.3.1.7.3 Timeout After Wakeup Signal and Timeout After Three Wakeup Signals
        8. 28.3.1.8  TXRX Error Detector (TED)
          1. 28.3.1.8.1 Bit Errors
          2. 28.3.1.8.2 Physical Bus Errors
          3. 28.3.1.8.3 ID Parity Errors
          4. 28.3.1.8.4 Checksum Errors
        9. 28.3.1.9  Message Filtering and Validation
        10. 28.3.1.10 Receive Buffers
        11. 28.3.1.11 Transmit Buffers
      2. 28.3.2 LIN Interrupts
      3. 28.3.3 Servicing LIN Interrupts
      4. 28.3.4 LIN DMA Interface
        1. 28.3.4.1 LIN Receive DMA Requests
        2. 28.3.4.2 LIN Transmit DMA Requests
      5. 28.3.5 LIN Configurations
        1. 28.3.5.1 Receiving Data
          1. 28.3.5.1.1 Receiving Data in Single-Buffer Mode
          2. 28.3.5.1.2 Receiving Data in Multibuffer Mode
        2. 28.3.5.2 Transmitting Data
          1. 28.3.5.2.1 Transmitting Data in Single-Buffer Mode
          2. 28.3.5.2.2 Transmitting Data in Multibuffer Mode
    4. 28.4 Low-Power Mode
      1. 28.4.1 Entering Sleep Mode
      2. 28.4.2 Wakeup
      3. 28.4.3 Wakeup Timeouts
    5. 28.5 Emulation Mode
    6. 28.6 Software
      1. 28.6.1 LIN Registers to Driverlib Functions
      2. 28.6.2 LIN Examples
        1. 28.6.2.1 LIN Internal Loopback with Interrupts
        2. 28.6.2.2 LIN SCI Mode Internal Loopback with Interrupts
        3. 28.6.2.3 LIN SCI MODE Internal Loopback with DMA
        4. 28.6.2.4 LIN Internal Loopback without interrupts(polled mode)
        5. 28.6.2.5 LIN SCI MODE (Single Buffer) Internal Loopback with DMA
    7. 28.7 LIN Registers
      1. 28.7.1 LIN Base Address Table
      2. 28.7.2 LIN_REGS Registers
  31. 29Configurable Logic Block (CLB)
    1. 29.1 Introduction
      1. 29.1.1 CLB Related Collateral
    2. 29.2 Description
      1. 29.2.1 CLB Clock
    3. 29.3 CLB Input/Output Connection
      1. 29.3.1 Overview
      2. 29.3.2 CLB Input Selection
      3. 29.3.3 CLB Output Selection
      4. 29.3.4 CLB Output Signal Multiplexer
    4. 29.4 CLB Tile
      1. 29.4.1 Static Switch Block
      2. 29.4.2 Counter Block
        1. 29.4.2.1 Counter Description
        2. 29.4.2.2 Counter Operation
        3. 29.4.2.3 Serializer Mode
        4. 29.4.2.4 Linear Feedback Shift Register (LFSR) Mode
      3. 29.4.3 FSM Block
      4. 29.4.4 LUT4 Block
      5. 29.4.5 Output LUT Block
      6. 29.4.6 Asynchronous Output Conditioning (AOC) Block
      7. 29.4.7 High Level Controller (HLC)
        1. 29.4.7.1 High Level Controller Events
        2. 29.4.7.2 High Level Controller Instructions
        3. 29.4.7.3 <Src> and <Dest>
        4. 29.4.7.4 Operation of the PUSH and PULL Instructions (Overflow and Underflow Detection)
    5. 29.5 CPU Interface
      1. 29.5.1 Register Description
      2. 29.5.2 Non-Memory Mapped Registers
    6. 29.6 DMA Access
    7. 29.7 CLB Data Export Through SPI RX Buffer
    8. 29.8 Software
      1. 29.8.1 CLB Registers to Driverlib Functions
      2. 29.8.2 CLBOUTPUTXBAR Registers to Driverlib Functions
      3. 29.8.3 CLBXBAR Registers to Driverlib Functions
      4. 29.8.4 CLB Examples
        1. 29.8.4.1  CLB Empty Project
        2. 29.8.4.2  CLB Combinational Logic
        3. 29.8.4.3  CLB GPIO Input Filter
        4. 29.8.4.4  CLB Auxilary PWM
        5. 29.8.4.5  CLB PWM Protection
        6. 29.8.4.6  CLB Event Window
        7. 29.8.4.7  CLB Signal Generator
        8. 29.8.4.8  CLB State Machine
        9. 29.8.4.9  CLB External Signal AND Gate
        10. 29.8.4.10 CLB Timer
        11. 29.8.4.11 CLB Timer Two States
        12. 29.8.4.12 CLB Interrupt Tag
        13. 29.8.4.13 CLB Output Intersect
        14. 29.8.4.14 CLB PUSH PULL
        15. 29.8.4.15 CLB Multi Tile
        16. 29.8.4.16 CLB Tile to Tile Delay
        17. 29.8.4.17 CLB Glue Logic
        18. 29.8.4.18 CLB based One-shot PWM
        19. 29.8.4.19 CLB AOC Control
        20. 29.8.4.20 CLB AOC Release Control
        21. 29.8.4.21 CLB XBARs
        22. 29.8.4.22 CLB AOC Control
        23. 29.8.4.23 CLB Serializer
        24. 29.8.4.24 CLB LFSR
        25. 29.8.4.25 CLB Lock Output Mask
        26. 29.8.4.26 CLB INPUT Pipeline Mode
        27. 29.8.4.27 CLB Clocking and PIPELINE Mode
        28. 29.8.4.28 CLB SPI Data Export
        29. 29.8.4.29 CLB SPI Data Export DMA
        30. 29.8.4.30 CLB Trip Zone Timestamp
        31. 29.8.4.31 CLB CRC
        32. 29.8.4.32 CLB TDM Serial Port
        33. 29.8.4.33 CLB LED Driver
    9. 29.9 CLB Registers
      1. 29.9.1 CLB Base Address Table
      2. 29.9.2 CLB_LOGIC_CONFIG_REGS Registers
      3. 29.9.3 CLB_LOGIC_CONTROL_REGS Registers
      4. 29.9.4 CLB_DATA_EXCHANGE_REGS Registers
  32. 30Advanced Encryption Standard (AES) Accelerator
    1. 30.1 Introduction
      1. 30.1.1 AES Block Diagram
        1. 30.1.1.1 Interfaces
        2. 30.1.1.2 AES Subsystem
        3. 30.1.1.3 AES Wide-Bus Engine
      2. 30.1.2 AES Algorithm
    2. 30.2 AES Operating Modes
      1. 30.2.1  GCM Operation
      2. 30.2.2  CCM Operation
      3. 30.2.3  XTS Operation
      4. 30.2.4  ECB Feedback Mode
      5. 30.2.5  CBC Feedback Mode
      6. 30.2.6  CTR and ICM Feedback Modes
      7. 30.2.7  CFB Mode
      8. 30.2.8  F8 Mode
      9. 30.2.9  F9 Operation
      10. 30.2.10 CBC-MAC Operation
    3. 30.3 Extended and Combined Modes of Operations
      1. 30.3.1 GCM Protocol Operation
      2. 30.3.2 CCM Protocol Operation
      3. 30.3.3 Hardware Requests
    4. 30.4 AES Module Programming Guide
      1. 30.4.1 AES Low-Level Programming Models
        1. 30.4.1.1 Global Initialization
        2. 30.4.1.2 AES Operating Modes Configuration
        3. 30.4.1.3 AES Mode Configurations
        4. 30.4.1.4 AES Events Servicing
    5. 30.5 Software
      1. 30.5.1 AES Registers to Driverlib Functions
      2. 30.5.2 AES_SS Registers to Driverlib Functions
      3. 30.5.3 AES Examples
        1. 30.5.3.1 AES ECB Encryption Example
        2. 30.5.3.2 AES ECB De-cryption Example
        3. 30.5.3.3 AES GCM Encryption Example
        4. 30.5.3.4 AES GCM Decryption Example
    6. 30.6 AES Registers
      1. 30.6.1 AES Base Address Table
      2. 30.6.2 AES_REGS Registers
      3. 30.6.3 AES_SS_REGS Registers
  33. 31Embedded Pattern Generator (EPG)
    1. 31.1 Introduction
      1. 31.1.1 Features
      2. 31.1.2 EPG Block Diagram
      3. 31.1.3 EPG Related Collateral
    2. 31.2 Clock Generator Modules
      1. 31.2.1 DCLK (50% duty cycle clock)
      2. 31.2.2 Clock Stop
    3. 31.3 Signal Generator Module
    4. 31.4 EPG Peripheral Signal Mux Selection
    5. 31.5 Application Software Notes
    6. 31.6 EPG Example Use Cases
      1. 31.6.1 EPG Example: Synchronous Clocks with Offset
        1. 31.6.1.1 Synchronous Clocks with Offset Register Configuration
      2. 31.6.2 EPG Example: Serial Data Bit Stream (LSB first)
        1. 31.6.2.1 Serial Data Bit Stream (LSB first) Register Configuration
      3. 31.6.3 EPG Example: Serial Data Bit Stream (MSB first)
        1. 31.6.3.1 Serial Data Bit Stream (MSB first) Register Configuration
    7. 31.7 EPG Interrupt
    8. 31.8 Software
      1. 31.8.1 EPG Registers to Driverlib Functions
      2. 31.8.2 EPG Examples
        1. 31.8.2.1 EPG Generating Synchronous Clocks
        2. 31.8.2.2 EPG Generating Two Offset Clocks
        3. 31.8.2.3 EPG Generating Two Offset Clocks With SIGGEN
        4. 31.8.2.4 EPG Generate Serial Data
        5. 31.8.2.5 EPG Generate Serial Data Shift Mode
    9. 31.9 EPG Registers
      1. 31.9.1 EPG Base Address Table
      2. 31.9.2 EPG_REGS Registers
      3. 31.9.3 EPG_MUX_REGS Registers
  34. 32Revision History

3.16.9 DEV_CFG_REGS Registers

Table 3-104 lists the memory-mapped registers for the DEV_CFG_REGS registers. All register offset addresses not listed in Table 3-104 should be considered as reserved locations and the register contents should not be modified.

Table 3-104 DEV_CFG_REGS Registers
OffsetAcronymRegister NameWrite ProtectionSection
8hPARTIDLLower 32-bit of Device PART Identification NumberGo
AhPARTIDHUpper 32-bit of Device PART Identification NumberGo
ChREVIDDevice Revision NumberGo
74hTRIMERRSTSTRIM Error Status registerGo
82hSOFTPRES0Processing Block Software Reset registerEALLOWGo
86hSOFTPRES2EPWM Software Reset registerEALLOWGo
88hSOFTPRES3ECAP Software Reset registerEALLOWGo
8AhSOFTPRES4EQEP Software Reset registerEALLOWGo
90hSOFTPRES7SCI Software Reset registerEALLOWGo
92hSOFTPRES8SPI Software Reset registerEALLOWGo
94hSOFTPRES9I2C Software Reset registerEALLOWGo
96hSOFTPRES10CAN Software Reset registerEALLOWGo
98hSOFTPRES11McBSP/USB Software Reset registerEALLOWGo
9ChSOFTPRES13ADC Software Reset registerEALLOWGo
9EhSOFTPRES14CMPSS Software Reset registerEALLOWGo
A0hSOFTPRES15PGA Software Reset registerEALLOWGo
A2hSOFTPRES16DAC Software Reset registerEALLOWGo
A4hSOFTPRES17CLB Software Reset registerEALLOWGo
A6hSOFTPRES18FSI Software Reset registerEALLOWGo
A8hSOFTPRES19LIN Software Reset registerEALLOWGo
AAhSOFTPRES20PMBUS Software Reset registerEALLOWGo
AChSOFTPRES21DCC Software Reset registerEALLOWGo
B6hSOFTPRES26AES Software Reset registerEALLOWGo
B8hSOFTPRES27EPG Software Reset registerEALLOWGo
BAhSOFTPRES28Flash Software Reset registerEALLOWGo
BEhSOFTPRES30NNPU Software reset registerEALLOWGo
130hTAP_STATUSStatus of JTAG State machine & Debugger ConnectGo
132hTAP_CONTROLDisable TAP controlGo
19AhUSBTYPEConfigures USB Type for the deviceEALLOWGo
19BhECAPTYPEConfigures ECAP Type for the deviceEALLOWGo
1A6hMCUCNF3MCU Configuration: ETPWMGo
1B0hMCUCNF8MCU Configuration: SCIGo
1B6hMCUCNF11MCU Configuration: CANGo
1B8hMCUCNF12MCU Configuration: McBSP_USBGo
1BChMCUCNF14MCU Configuration: ADCGo
1C0hMCUCNF16MCU Configuration: PGAGo
1C4hMCUCNF18MCU Configuration: Lx.1 SRAM CustomizationGo
1C8hMCUCNF20MCU Configuration: GSx SRAM CustomizationGo
1CAhMCUCNF21MCU Configuration: CLBGo
1CEhMCUCNF23MCU Configuration: LINGo
1DEhMCUCNF31MCU Configuration: Flash Bank0Go
1E0hMCUCNF32MCU Configuration: Flash Bank1Go
1E2hMCUCNF33MCU Configuration: Flash Bank2Go
1E4hMCUCNF34MCU Configuration: Flash Bank3Go
1E6hMCUCNF35MCU Configuration: Flash Bank4Go
1F8hMCUCNFLOCKLock bit for MCUCNFx registersEALLOWGo

Complex bit access types are encoded to fit into small table cells. Table 3-105 shows the codes that are used for access types in this section.

Table 3-105 DEV_CFG_REGS Access Type Codes
Access TypeCodeDescription
Read Type
RRRead
R-0R
-0		Read
Returns 0s
Write Type
WWWrite
W1CW
1C		Write
1 to clear
W1SW
1S		Write
1 to set
WOnceW
Once		Write
Write once
WSonceW
Sonce		Write
Set once
Reset or Default Value
-nValue after reset or the default value
Register Array Variables
i,j,k,l,m,nWhen these variables are used in a register name, an offset, or an address, they refer to the value of a register array where the register is part of a group of repeating registers. The register groups form a hierarchical structure and the array is represented with a formula.
yWhen this variable is used in a register name, an offset, or an address it refers to the value of a register array.

3.16.9.1 PARTIDL Register (Offset = 8h) [Reset = 00XXXXX0h]

PARTIDL is shown in Figure 3-85 and described in Table 3-106.

Return to the Summary Table.

Lower 32-bit of Device PART Identification Number

Figure 3-85 PARTIDL Register
3130292827262524
RESERVEDRESERVED
R-0hR-0h
2322212019181716
FLASH_SIZE
R-X
15141312111098
RESERVEDINSTASPINRESERVEDRESERVEDPIN_COUNT
R-0hR-XR-0hR-XR-X
76543210
QUALRESERVEDRESERVEDRESERVED
R-XR-0hR-0hR-0h
Table 3-106 PARTIDL Register Field Descriptions
BitFieldTypeResetDescription
31-28RESERVEDR0hReserved
27-24RESERVEDR0hReserved
23-16FLASH_SIZERX0x8 - 1088KB
0x7 - 1024KB
0x6 - 576KB
0x5 - 512KB
0x4 - 256KB
0x3 -128KB
0x0-0x2 - Reserved

Reset type: PORESETn

15RESERVEDR0hReserved
14-13INSTASPINRX1 = InstaSPIN-FOC
2 = NONE
3 = NONE

Reset type: PORESETn

12RESERVEDR0hReserved
11RESERVEDRXReserved
10-8PIN_COUNTRX0 = 56 pin QFN
1 = 64 pin QFP
2 = 80 pin QFP
3 = 100 pin QFP
4 = 128 pin QFP
5 = Reserved
6 = Reserved
7 = Reserved

Reset type: PORESETn

7-6QUALRX0 = Engineering sample (TMX)
1 = Pilot production (TMP)
2 = Fully qualified (TMS)

Reset type: PORESETn

5RESERVEDR0hReserved
4-3RESERVEDR0hReserved
2-0RESERVEDR0hReserved

3.16.9.2 PARTIDH Register (Offset = Ah) [Reset = 09XX0500h]

PARTIDH is shown in Figure 3-86 and described in Table 3-107.

Return to the Summary Table.

Upper 32-bit of Device PART Identification Number

Figure 3-86 PARTIDH Register
31302928272625242322212019181716
DEVICE_CLASS_IDPARTNO
R-9hR-X
1514131211109876543210
FAMILYRESERVEDRESERVED
R-5hR-0hR-0h
Table 3-107 PARTIDH Register Field Descriptions
BitFieldTypeResetDescription
31-24DEVICE_CLASS_IDR9hDevice class ID

Reset type: PORESETn

23-16PARTNORXRefer to Datasheet for Device Part Number

Reset type: PORESETn

15-8FAMILYR5hDevice Family

Reset type: PORESETn

7-4RESERVEDR0hReserved
3-0RESERVEDR0hReserved

3.16.9.3 REVID Register (Offset = Ch) [Reset = 00000000h]

REVID is shown in Figure 3-87 and described in Table 3-108.

Return to the Summary Table.

Device Revision Number

Figure 3-87 REVID Register
31302928272625242322212019181716
RESERVED
R-0-0h
1514131211109876543210
REVID_EXTREVID
R-0hR/WOnce-0h
Table 3-108 REVID Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-8REVID_EXTR0hDevice Revision ID extension.

Reset type: XRSn

7-0REVIDR/WOnce0hDevice Revision ID. Loaded from flash trim sector by boot rom. Reset value is die-specific.

Reset type: XRSn

3.16.9.4 TRIMERRSTS Register (Offset = 74h) [Reset = 00000000h]

TRIMERRSTS is shown in Figure 3-88 and described in Table 3-109.

Return to the Summary Table.

TRIM Error Status register

Figure 3-88 TRIMERRSTS Register
313029282726252423222120191817161514131211109876543210
RESERVEDLERR
R-0-0hR/WSonce-0h
Table 3-109 TRIMERRSTS Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-0LERRR/WSonce0hTRIM information load error status. This will include error during SRAM repair also.

00000: No error during load
Other: Non zero value indicates error during load

Note:
[1] This bit is updated by software. Details will be filled in once the Boot ROM related requirements are complete. It should have bits to indicate
(i) Double bit error during trim load
(ii) Single bit error during trim load
(iii) Double bit error during SRAM repair load
(iv) Single bit error error during SRAM repair load
(v) SRAM repair error load (chain is broken)
(vi) PWRUPSTS.TRIMOVER signal is not asserted even after the full wait time

Reset type: XRSn

3.16.9.5 SOFTPRES0 Register (Offset = 82h) [Reset = 00000000h]

SOFTPRES0 is shown in Figure 3-89 and described in Table 3-110.

Return to the Summary Table.

Processing Block Software Reset register
When bits in this register are set, the respective module is in reset. All design data is lost and the module registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-89 SOFTPRES0 Register
3130292827262524
RESERVEDCPU1_ERAD
R-0-0hR/W-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDCPU1_CLA1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-110 SOFTPRES0 Register Field Descriptions
BitFieldTypeResetDescription
31-25RESERVEDR-00hReserved
24CPU1_ERADR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

23-16RESERVEDR-00hReserved
15RESERVEDR-00hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0CPU1_CLA1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.6 SOFTPRES2 Register (Offset = 86h) [Reset = 00000000h]

SOFTPRES2 is shown in Figure 3-90 and described in Table 3-111.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-90 SOFTPRES2 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDEPWM12EPWM11EPWM10EPWM9
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-111 SOFTPRES2 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDR/W0hReserved
14RESERVEDR/W0hReserved
13RESERVEDR/W0hReserved
12RESERVEDR/W0hReserved
11EPWM12R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

10EPWM11R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

9EPWM10R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

8EPWM9R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

7EPWM8R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

6EPWM7R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

5EPWM6R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

4EPWM5R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3EPWM4R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

2EPWM3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

1EPWM2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0EPWM1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.7 SOFTPRES3 Register (Offset = 88h) [Reset = 00000000h]

SOFTPRES3 is shown in Figure 3-91 and described in Table 3-112.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-91 SOFTPRES3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDECAP2ECAP1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-112 SOFTPRES3 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1ECAP2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0ECAP1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.8 SOFTPRES4 Register (Offset = 8Ah) [Reset = 00000000h]

SOFTPRES4 is shown in Figure 3-92 and described in Table 3-113.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-92 SOFTPRES4 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDEQEP3EQEP2EQEP1
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-113 SOFTPRES4 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2EQEP3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

1EQEP2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure
Note: This bit is applicable only for Topoauto

Reset type: SYSRSn

0EQEP1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.9 SOFTPRES7 Register (Offset = 90h) [Reset = 00000000h]

SOFTPRES7 is shown in Figure 3-93 and described in Table 3-114.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-93 SOFTPRES7 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDSCI_CSCI_BSCI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-114 SOFTPRES7 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2SCI_CR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

1SCI_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0SCI_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.10 SOFTPRES8 Register (Offset = 92h) [Reset = 00000000h]

SOFTPRES8 is shown in Figure 3-94 and described in Table 3-115.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-94 SOFTPRES8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDSPI_BSPI_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-115 SOFTPRES8 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16RESERVEDR/W0hReserved
15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1SPI_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0SPI_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.11 SOFTPRES9 Register (Offset = 94h) [Reset = 00000000h]

SOFTPRES9 is shown in Figure 3-95 and described in Table 3-116.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-95 SOFTPRES9 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDI2C_BI2C_A
R-0-0hR/W-0hR/W-0h
Table 3-116 SOFTPRES9 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1I2C_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0I2C_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.12 SOFTPRES10 Register (Offset = 96h) [Reset = 000000X0h]

SOFTPRES10 is shown in Figure 3-96 and described in Table 3-117.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-96 SOFTPRES10 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDMCAN_BMCAN_ARESERVEDRESERVEDRESERVEDRESERVED
R-XR-XR-XR-XR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-117 SOFTPRES10 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5MCAN_BRX1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

4MCAN_ARX1: Module is under reset
0: Module reset is determined by the normal device reset structure
Note: This bit is applicable only for Topoauto

Reset type: SYSRSn

3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.16.9.13 SOFTPRES11 Register (Offset = 98h) [Reset = 00000000h]

SOFTPRES11 is shown in Figure 3-97 and described in Table 3-118.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-97 SOFTPRES11 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDUSB_A
R-0-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0h
Table 3-118 SOFTPRES11 Register Field Descriptions
BitFieldTypeResetDescription
31-18RESERVEDR-00hReserved
17RESERVEDR/W0hReserved
16USB_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

15-2RESERVEDR-00hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.16.9.14 SOFTPRES13 Register (Offset = 9Ch) [Reset = 00000000h]

SOFTPRES13 is shown in Figure 3-98 and described in Table 3-119.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-98 SOFTPRES13 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDADC_EADC_DADC_CADC_BADC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-119 SOFTPRES13 Register Field Descriptions
BitFieldTypeResetDescription
31-5RESERVEDR-00hReserved
4ADC_ER/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3ADC_DR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

2ADC_CR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

1ADC_BR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0ADC_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.15 SOFTPRES14 Register (Offset = 9Eh) [Reset = 00000000h]

SOFTPRES14 is shown in Figure 3-99 and described in Table 3-120.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-99 SOFTPRES14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDCMPSS4CMPSS3CMPSS2CMPSS1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-120 SOFTPRES14 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3CMPSS4R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

2CMPSS3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

1CMPSS2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0CMPSS1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.16 SOFTPRES15 Register (Offset = A0h) [Reset = 00000000h]

SOFTPRES15 is shown in Figure 3-100 and described in Table 3-121.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-100 SOFTPRES15 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDPGA3PGA2PGA1
R/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-121 SOFTPRES15 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDR/W0hReserved
6RESERVEDR/W0hReserved
5RESERVEDR/W0hReserved
4RESERVEDR/W0hReserved
3RESERVEDR/W0hReserved
2PGA3R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

1PGA2R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0PGA1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.17 SOFTPRES16 Register (Offset = A2h) [Reset = 00000000h]

SOFTPRES16 is shown in Figure 3-101 and described in Table 3-122.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-101 SOFTPRES16 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVEDRESERVEDDAC_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-122 SOFTPRES16 Register Field Descriptions
BitFieldTypeResetDescription
31-20RESERVEDR-00hReserved
19RESERVEDR/W0hReserved
18RESERVEDR/W0hReserved
17RESERVEDR/W0hReserved
16DAC_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

15-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0RESERVEDR/W0hReserved

3.16.9.18 SOFTPRES17 Register (Offset = A4h) [Reset = 0000000Xh]

SOFTPRES17 is shown in Figure 3-102 and described in Table 3-123.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-102 SOFTPRES17 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDCLB2CLB1
R-0hR/W-0hR/W-0hR-XR-X
Table 3-123 SOFTPRES17 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1CLB2RX1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0CLB1RX1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.19 SOFTPRES18 Register (Offset = A6h) [Reset = 0000000Xh]

SOFTPRES18 is shown in Figure 3-103 and described in Table 3-124.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-103 SOFTPRES18 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDFSIRX_AFSITX_A
R-0hR/W-0hR/W-0hR-XR-X
Table 3-124 SOFTPRES18 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1FSIRX_ARX1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0FSITX_ARX1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.20 SOFTPRES19 Register (Offset = A8h) [Reset = 00000000h]

SOFTPRES19 is shown in Figure 3-104 and described in Table 3-125.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-104 SOFTPRES19 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDLIN_A
R-0-0hR/W-0hR/W-0hR/W-0hR/W-0h
Table 3-125 SOFTPRES19 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDR/W0hReserved
2RESERVEDR/W0hReserved
1RESERVEDR/W0hReserved
0LIN_AR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure
Note: This bit is applicable only for Topoauto

Reset type: SYSRSn

3.16.9.21 SOFTPRES20 Register (Offset = AAh) [Reset = 00000000h]

SOFTPRES20 is shown in Figure 3-105 and described in Table 3-126.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-105 SOFTPRES20 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDPMBUS_A
R-0hR-0hR-0h
Table 3-126 SOFTPRES20 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR0hReserved
1RESERVEDR0hReserved
0PMBUS_AR0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.22 SOFTPRES21 Register (Offset = ACh) [Reset = 00000000h]

SOFTPRES21 is shown in Figure 3-106 and described in Table 3-127.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-106 SOFTPRES21 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDDCC1DCC0
R-0-0hR/W-0hR/W-0h
Table 3-127 SOFTPRES21 Register Field Descriptions
BitFieldTypeResetDescription
31-2RESERVEDR-00hReserved
1DCC1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

0DCC0R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.23 SOFTPRES26 Register (Offset = B6h) [Reset = 00000000h]

SOFTPRES26 is shown in Figure 3-107 and described in Table 3-128.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-107 SOFTPRES26 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDAESA
R-0-0hR/W-0h
Table 3-128 SOFTPRES26 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0AESAR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.24 SOFTPRES27 Register (Offset = B8h) [Reset = 00000000h]

SOFTPRES27 is shown in Figure 3-108 and described in Table 3-129.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-108 SOFTPRES27 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDEPG1
R-0-0hR/W-0h
Table 3-129 SOFTPRES27 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0EPG1R/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.25 SOFTPRES28 Register (Offset = BAh) [Reset = 00000000h]

SOFTPRES28 is shown in Figure 3-109 and described in Table 3-130.

Return to the Summary Table.

Peripheral Software Reset register

When bits in this register are set, the respective peripheral is in reset. All data is lost and the peripheral registers are returned to their reset states. Bits must be manually cleared after being set.

Figure 3-109 SOFTPRES28 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDFLASHA
R-0-0hR/W-0h
Table 3-130 SOFTPRES28 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0FLASHAR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Note: Whenever the reset to flash is asserted, it will be internally stretched to ~15us

Reset type: SYSRSn

3.16.9.26 SOFTPRES30 Register (Offset = BEh) [Reset = 00000000h]

SOFTPRES30 is shown in Figure 3-110 and described in Table 3-131.

Return to the Summary Table.

NNPU Software reset register

Figure 3-110 SOFTPRES30 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDNNPU
R-0-0hR/W-0h
Table 3-131 SOFTPRES30 Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0NNPUR/W0h1: Module is under reset
0: Module reset is determined by the normal device reset structure

Reset type: SYSRSn

3.16.9.27 TAP_STATUS Register (Offset = 130h) [Reset = 00000000h]

TAP_STATUS is shown in Figure 3-111 and described in Table 3-132.

Return to the Summary Table.

Status of JTAG State machine & Debugger Connect

Figure 3-111 TAP_STATUS Register
3130292827262524
DCONRESERVED
R-0hR-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
TAP_STATE
R-0h
76543210
TAP_STATE
R-0h
Table 3-132 TAP_STATUS Register Field Descriptions
BitFieldTypeResetDescription
31DCONR0hDebugConnect indication from IcePick.

Reset type: PORESETn

30-16RESERVEDR-00hReserved
15-0TAP_STATER0hTAP State Vector. With bits representing, Connect coresponding POTAP* output to the
0:TLR,
1:IDLE,
2:SELECTDR,
3:CAPDR,
4:SHIFTDR,
5:EXIT1DR,
6:PAUSEDR,
7:EXIT2DR,
8:UPDTDR,
9:SLECTIR,
10:CAPIR,
11:SHIFTIR,
12:EXIT1IR,
13:PAUSEIR,
14:EXIT2IR,
15:UPDTIR,

Reset type: PORESETn

3.16.9.28 TAP_CONTROL Register (Offset = 132h) [Reset = 00000000h]

TAP_CONTROL is shown in Figure 3-112 and described in Table 3-133.

Return to the Summary Table.

Disable TAP control

Figure 3-112 TAP_CONTROL Register
3130292827262524
KEY
R-0/W-0h
2322212019181716
KEY
R-0/W-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDBSCAN_DIS
R-0-0hR/W-0h
Table 3-133 TAP_CONTROL Register Field Descriptions
BitFieldTypeResetDescription
31-16KEYR-0/W0hWrite to this register succeeds only if this field is written with a value of 0xa5a5

Note:
[1] Due to this KEY, only 32-bit writes will succeed (provided the KEY matches). 16-bit writes to the upper or lower half of this register will be ignored

Reset type: PORESETn

15-1RESERVEDR-00hReserved
0BSCAN_DISR/W0hDisables BSCAN TAP control :

0: BSCAN TAP control enabled
1: BSCAN TAP control disabled

Reset type: PORESETn

3.16.9.29 USBTYPE Register (Offset = 19Ah) [Reset = 0000h]

USBTYPE is shown in Figure 3-113 and described in Table 3-134.

Return to the Summary Table.

Based on the configuration enables disables features associated with the USB type.

Figure 3-113 USBTYPE Register
15141312111098
LOCKRESERVED
R/WSonce-0hR-0-0h
76543210
RESERVEDTYPE
R-0-0hR/W-0h
Table 3-134 USBTYPE Register Field Descriptions
BitFieldTypeResetDescription
15LOCKR/WSonce0h1: Write to this register is not allowed.
0: Write to this register is allowed.

Reset type: CPU1.SYSRSn

14-2RESERVEDR-00hReserved
1-0TYPER/W0h'00,10,11' :
1. Global interrupt feature is not enabled, interrupts fired unconditionally.
'01' :
1.Global interrupt feature is enabled, refer to the spec doc for more details about global interrupt feature.

Reset type: CPU1.SYSRSn

3.16.9.30 ECAPTYPE Register (Offset = 19Bh) [Reset = 0000h]

ECAPTYPE is shown in Figure 3-114 and described in Table 3-135.

Return to the Summary Table.

Based on the configuration enables disables features associated with the ECAP type.

Figure 3-114 ECAPTYPE Register
15141312111098
LOCKRESERVED
R/WSonce-0hR-0-0h
76543210
RESERVEDTYPE
R-0-0hR/W-0h
Table 3-135 ECAPTYPE Register Field Descriptions
BitFieldTypeResetDescription
15LOCKR/WSonce0h1: Write to this register is not allowed.
0: Write to this register is allowed.

Reset type: SYSRSn

14-2RESERVEDR-00hReserved
1-0TYPER/W0h'00,10,11' :
1. No EALLOW protection to ECAP registers.
'01' :
1. ECAP registers are EALLOW protected.

Reset type: SYSRSn

3.16.9.31 MCUCNF3 Register (Offset = 1A6h) [Reset = 0000XXXXh]

MCUCNF3 is shown in Figure 3-115 and described in Table 3-136.

Return to the Summary Table.

MCU Configuration: ETPWM

Figure 3-115 MCUCNF3 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDEPWM12EPWM11EPWM10EPWM9
R-XR-XR-XR-XR-XR-XR-XR-X
76543210
EPWM8EPWM7EPWM6EPWM5EPWM4EPWM3EPWM2EPWM1
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-136 MCUCNF3 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDRXReserved
14RESERVEDRXReserved
13RESERVEDRXReserved
12RESERVEDRXReserved
11EPWM12RXEPWM12 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

10EPWM11RXEPWM11 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

9EPWM10RXEPWM10 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

8EPWM9RXEPWM9 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

7EPWM8RXEPWM8 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

6EPWM7RXEPWM7 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

5EPWM6RXEPWM6 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4EPWM5RXEPWM5 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3EPWM4RXEPWM4 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2EPWM3RXEPWM3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1EPWM2RXEPWM2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0EPWM1RXEPWM1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.16.9.32 MCUCNF8 Register (Offset = 1B0h) [Reset = 0000000Xh]

MCUCNF8 is shown in Figure 3-116 and described in Table 3-137.

Return to the Summary Table.

MCU Configuration: SCI

Figure 3-116 MCUCNF8 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDSCI_CSCI_BSCI_A
R-0-0hR-XR-XR-XR-X
Table 3-137 MCUCNF8 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR-00hReserved
3RESERVEDRXReserved
2SCI_CRXSCI_C :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1SCI_BRXSCI_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0SCI_ARXSCI_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.16.9.33 MCUCNF11 Register (Offset = 1B6h) [Reset = 000000XXh]

MCUCNF11 is shown in Figure 3-117 and described in Table 3-138.

Return to the Summary Table.

MCU Configuration: CAN

Figure 3-117 MCUCNF11 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDMCAN_BMCAN_ARESERVEDRESERVEDRESERVEDRESERVED
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-138 MCUCNF11 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5MCAN_BRXMCAN_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4MCAN_ARXMCAN_A :
0: Feature not present on the device
1: Feature present on the device
Note: This bit is applicable only for Topoauto

Reset type: PORESETn

3RESERVEDRXReserved
2RESERVEDRXReserved
1RESERVEDRXReserved
0RESERVEDRXReserved

3.16.9.34 MCUCNF12 Register (Offset = 1B8h) [Reset = 000X000Xh]

MCUCNF12 is shown in Figure 3-118 and described in Table 3-139.

Return to the Summary Table.

MCU Configuration: McBSP_USB

Figure 3-118 MCUCNF12 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVEDRESERVEDRESERVEDUSB_A
R-0-0hR-XR-0-0hR-X
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVED
R-0-0hR-XR-X
Table 3-139 MCUCNF12 Register Field Descriptions
BitFieldTypeResetDescription
31-19RESERVEDR-00hReserved
18RESERVEDRXReserved
17RESERVEDR-00hReserved
16USB_ARXUSB_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

15-2RESERVEDR-00hReserved
1RESERVEDRXReserved
0RESERVEDRXReserved

3.16.9.35 MCUCNF14 Register (Offset = 1BCh) [Reset = 000000XXh]

MCUCNF14 is shown in Figure 3-119 and described in Table 3-140.

Return to the Summary Table.

MCU Configuration: ADC

Figure 3-119 MCUCNF14 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDADC_EADC_DADC_CADC_BADC_A
R-0-0hR-XR-XR-XR-XR-X
Table 3-140 MCUCNF14 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15-5RESERVEDR-00hReserved
4ADC_ERXADC_E :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3ADC_DRXADC_D :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2ADC_CRXADC_C :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1ADC_BRXADC_B :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0ADC_ARXADC_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.16.9.36 MCUCNF16 Register (Offset = 1C0h) [Reset = 000000XXh]

MCUCNF16 is shown in Figure 3-120 and described in Table 3-141.

Return to the Summary Table.

MCU Configuration: PGA

Figure 3-120 MCUCNF16 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDPGA3PGA2PGA1
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-141 MCUCNF16 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5RESERVEDRXReserved
4RESERVEDRXReserved
3RESERVEDRXReserved
2PGA3RXPGA3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1PGA2RXPGA2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0PGA1RXPGA1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.16.9.37 MCUCNF18 Register (Offset = 1C4h) [Reset = 00000XXXh]

MCUCNF18 is shown in Figure 3-121 and described in Table 3-142.

Return to the Summary Table.

MCU Configuration: Lx.1 SRAM Customization

Figure 3-121 MCUCNF18 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDLS9_1LS8_1
R-0-0hR-XR-X
76543210
LS7_1LS6_1LS5_1LS4_1LS3_1LS2_1LS1_1LS0_1
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-142 MCUCNF18 Register Field Descriptions
BitFieldTypeResetDescription
31-10RESERVEDR-00hReserved
9LS9_1RXLS9_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

8LS8_1RXLS8_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

7LS7_1RXLS7_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

6LS6_1RXLS6_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

5LS5_1RXLS5_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

4LS4_1RXLS4_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3LS3_1RXLS3_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2LS2_1RXLS2_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1LS1_1RXLS1_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0LS0_1RXLS0_1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.16.9.38 MCUCNF20 Register (Offset = 1C8h) [Reset = 0000XXXXh]

MCUCNF20 is shown in Figure 3-122 and described in Table 3-143.

Return to the Summary Table.

MCU Configuration: GSx SRAM Customization

Figure 3-122 MCUCNF20 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVED
R-XR-XR-XR-XR-XR-XR-XR-X
76543210
RESERVEDRESERVEDRESERVEDRESERVEDGS3GS2GS1GS0
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-143 MCUCNF20 Register Field Descriptions
BitFieldTypeResetDescription
31-16RESERVEDR-00hReserved
15RESERVEDRXReserved
14RESERVEDRXReserved
13RESERVEDRXReserved
12RESERVEDRXReserved
11RESERVEDRXReserved
10RESERVEDRXReserved
9RESERVEDRXReserved
8RESERVEDRXReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5RESERVEDRXReserved
4RESERVEDRXReserved
3GS3RXGS3 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

2GS2RXGS2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

1GS1RXGS1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0GS0RXGS0 :
0: Feature not present on the device
1: Feature present on the device

Note: This applies to upper 8KB of GS0 only. Lower 8KB is always available and not affected by this bit value.

Reset type: PORESETn

3.16.9.39 MCUCNF21 Register (Offset = 1CAh) [Reset = 00000000h]

MCUCNF21 is shown in Figure 3-123 and described in Table 3-144.

Return to the Summary Table.

MCU Configuration: CLB

Figure 3-123 MCUCNF21 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDCLB2CLB1
R-0hR-0hR-0hR-0hR-0h
Table 3-144 MCUCNF21 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1CLB2R0hCLB2 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

0CLB1R0hCLB1 :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.16.9.40 MCUCNF23 Register (Offset = 1CEh) [Reset = 00000000h]

MCUCNF23 is shown in Figure 3-124 and described in Table 3-145.

Return to the Summary Table.

MCU Configuration: LIN

Figure 3-124 MCUCNF23 Register
3130292827262524
RESERVED
R-0h
2322212019181716
RESERVED
R-0h
15141312111098
RESERVED
R-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDLIN_A
R-0hR-0hR-0hR-0hR-0h
Table 3-145 MCUCNF23 Register Field Descriptions
BitFieldTypeResetDescription
31-4RESERVEDR0hReserved
3RESERVEDR0hReserved
2RESERVEDR0hReserved
1RESERVEDR0hReserved
0LIN_AR0hLIN_A :
0: Feature not present on the device
1: Feature present on the device

Reset type: PORESETn

3.16.9.41 MCUCNF31 Register (Offset = 1DEh) [Reset = 000000XXh]

MCUCNF31 is shown in Figure 3-125 and described in Table 3-146.

Return to the Summary Table.

MCU Configuration: Flash Bank0

Figure 3-125 MCUCNF31 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-146 MCUCNF31 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7SECT127_112RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXFlash Bank-0:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.16.9.42 MCUCNF32 Register (Offset = 1E0h) [Reset = 000000XXh]

MCUCNF32 is shown in Figure 3-126 and described in Table 3-147.

Return to the Summary Table.

MCU Configuration: Flash Bank1

Figure 3-126 MCUCNF32 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-147 MCUCNF32 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7SECT127_112RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXFlash Bank-1:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.16.9.43 MCUCNF33 Register (Offset = 1E2h) [Reset = 000000XXh]

MCUCNF33 is shown in Figure 3-127 and described in Table 3-148.

Return to the Summary Table.

MCU Configuration: Flash Bank2

Figure 3-127 MCUCNF33 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-148 MCUCNF33 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7SECT127_112RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXFlash Bank-2:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.16.9.44 MCUCNF34 Register (Offset = 1E4h) [Reset = 000000XXh]

MCUCNF34 is shown in Figure 3-128 and described in Table 3-149.

Return to the Summary Table.

MCU Configuration: Flash Bank3

Figure 3-128 MCUCNF34 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
SECT127_112SECT111_96SECT95_80SECT79_64SECT63_48SECT47_32SECT31_16SECT15_0
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-149 MCUCNF34 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7SECT127_112RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

6SECT111_96RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

5SECT95_80RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

4SECT79_64RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3SECT63_48RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

2SECT47_32RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

1SECT31_16RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXFlash Bank-3:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.16.9.45 MCUCNF35 Register (Offset = 1E6h) [Reset = 000000XXh]

MCUCNF35 is shown in Figure 3-129 and described in Table 3-150.

Return to the Summary Table.

MCU Configuration: Flash Bank4

Figure 3-129 MCUCNF35 Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDRESERVEDRESERVEDRESERVEDRESERVEDRESERVEDSECT31_16SECT15_0
R-XR-XR-XR-XR-XR-XR-XR-X
Table 3-150 MCUCNF35 Register Field Descriptions
BitFieldTypeResetDescription
31-8RESERVEDR-00hReserved
7RESERVEDRXReserved
6RESERVEDRXReserved
5RESERVEDRXReserved
4RESERVEDRXReserved
3RESERVEDRXReserved
2RESERVEDRXReserved
1SECT31_16RXFlash Bank-4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

0SECT15_0RXFlash Bank-4:
0: Respective sectors are not present in the device
1: Respective sectors are present in the device

Reset type: PORESETn

3.16.9.46 MCUCNFLOCK Register (Offset = 1F8h) [Reset = 00000000h]

MCUCNFLOCK is shown in Figure 3-130 and described in Table 3-151.

Return to the Summary Table.

Lock bit for MCUCNFx registers
The locking mechanism applies to only writes. Reads to the registers which have LOCK protection are always allowed
Note:
Any SOnce bit in this register, once set can only be cleared through a CPU1.SYSRSn. Write of 0 to any bit of this register has no effect

Figure 3-130 MCUCNFLOCK Register
3130292827262524
RESERVED
R-0-0h
2322212019181716
RESERVED
R-0-0h
15141312111098
RESERVED
R-0-0h
76543210
RESERVEDMCUCNFLOCK
R-0-0hR/WSonce-0h
Table 3-151 MCUCNFLOCK Register Field Descriptions
BitFieldTypeResetDescription
31-1RESERVEDR-00hReserved
0MCUCNFLOCKR/WSonce0hLock bit for all MCUCNF registers:
0: Registers are not locked
1: Register are locked

Reset type: CPU1.SYSRSn