SPRUJ53 April 2024 TMS320F28P550SJ , TMS320F28P559SJ-Q1
Table 3-7 shows the clock connections sorted by the clock domain and Table 3-8 shows the clock connections sorted by the module name.
Clock Domain | Module Name |
---|---|
CPUCLK | FPU |
TMU | |
SYSCLK | ePIE |
Boot ROM | |
CAN Bit Clock | |
DCSM | |
Flash | |
GPIO Input Sync and Qual | |
GSx RAMs | |
LSx RAMs | |
Mx RAMs | |
WD | |
XINT | |
PLLCLK | CLB REG Clock |
CLB TILE Clock | |
USB Bit Clock | |
PLLSYSCLK | CPU |
NMIWD | |
PERx.SYSCLK | ADCA, B, C, D, E |
AES | |
CLB | |
CMPSS1-4 | |
DCC0-1 | |
eCAP1 - 2 | |
ePWM1 - 12 | |
eQEP1 - 3 | |
EPG | |
ERAD | |
FSI | |
GPDACA | |
HRCAL | |
I2CA, B | |
MCANA, B | |
PGA1-3 | |
PMBUSA | |
Timer0 - 2 | |
PERx.LSPCLK | SCIA, B, C |
SPIA, B | |
LINACLK | LINA |
CAN Bit Clock | MCANA, B |
USB Bit Clock | USB |
WDCLK (INTOSC1) | Watchdog Timer |
Module Name | Clock Domain |
---|---|
ADCA,B,C,D,E | PERx.SYSCLK |
AES | PERx.SYSCLK |
Boot ROM | SYSCLK |
CAN Bit Clock | SYSCLK |
CLB | PERx.SYSCLK |
CLB_REG_CLK | PLLCLK |
CLB_TILE_CLK | PLLCLK |
CMPSS1-4 | PERx.SYSCLK |
CPU | PLLSYSCLK |
CPU Timers (0 - 2) | PERx.SYSCLK |
DCC0 | PERx.SYSCLK |
DCSM | SYSCLK |
eCAP1 - 2 | PERx.SYSCLK |
ePIE | SYSCLK |
ePWM1 - 12 | PERx.SYSCLK |
eQEP1-3 | PERx.SYSCLK |
EPG | PERx.SYSCLK |
ERAD | PERx.SYSCLK |
Flash | SYSCLK |
FPU | CPUCLK |
FSI | PERx.SYSCLK |
GPDAC | PERx.SYSCLK |
GPIO Input Sync and Qual | SYSCLK |
GSx RAMs | SYSCLK |
I2CA - B | PERx.SYSCLK |
LINA | LINACLK |
LSx RAMs | SYSCLK |
Mx RAMs | SYSCLK |
MCANA,B | PERx.SYSCLK |
NMIWD | PLLSYSCLK |
SCIA - C | PERx.LSPCLK |
SPIA, B | PERx.LSPCLK |
TMU | CPUCLK |
USB | USBBITCLK |
USB Bit Clock | PLLCLK |
Watchdog Timer | WDCLK (INTOSC1) |