Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs - LMK04906

LMK04906 (ACTIVE)

Ultra Low Noise Clock Jitter Cleaner/Multiplier with 6 Programmable Outputs

Recommended alternative parts

  • LMK03806  - The device has SIMILAR FUNCTIONALITY but is not functionally equivalent to the compared device. 
  • LMK00301  -  10 Output Universal Fan Out Buffer from the LMK04906 clock generator
  • LMK00304  -  4 Output Universal Fan Out Buffer from the LMK04906 clock generator
  • LMK00306  -  6 Output Universal Fan Out Buffer from the LMK04906 clock generator
  • LMK00308  -  8 Output Universal Fan Out Buffer from the LMK04906 clock generator
  • LMK00101  -  10 Output Universal Fan Out Buffer from the LMK04906 clock generator

Description

The LMK04906 is the industry's highest performance clock jitter attenuator with superior clock jitter cleaning, generation, and distribution with advanced features to meet high performance timing application needs.

The LMK04906 accepts 3 clock input ranging from 1 kHz to 750 MHz and generates 6 unique clock output frequencies ranging from 2.26 MHz to 2.6 GHz. The LMK04906 can also buffer a crystal or VCXO to generate a 7th unique clock frequency.

The device provides virtually all frequency translation combination required for SONET, Ethernet, Fibre Channel and multi-mode Wireless Base Stations.

The LMK04906 input clock frequency and clock multiplication ratio are programmable through a SPI interface.

Features

  • Ultra-Low RMS Jitter Performance
    • 100 fs RMS Jitter (12 kHz to 20 MHz)
    • 123 fs RMS Jitter (100 Hz to 20 MHz)
  • Dual Loop PLLatinum PLL Architecture
    • PLL1
      • Integrated Low-Noise Crystal Oscillator Circuit
      • Holdover Mode when Input Clocks are Lost
        • Automatic or Manual Triggering/Recovery
    • PLL2
      • Normalized [1 Hz] PLL Noise Floor of -227 dBc/Hz
      • Phase Detector Rate up to 155 MHz
      • OSCin Frequency-doubler
      • Integrated Low-Noise VCO
  • 3 Redundant Input Clocks with LOS
    • Automatic and Manual Switch-Over Modes
  • 50% Duty Cycle Output Divides, 1 to 1045 (Even and Odd)
  • LVPECL, LVDS, or LVCMOS Programmable Outputs
  • Precision Digital Delay, Fixed or Dynamically Adjustable
  • 25 ps Step Analog Delay Control.
  • 6 Differential Outputs. Up to 12 Single Ended.
    • Up to 5 VCXO/Crystal Buffered Outputs
  • Clock Rates of up to 2600 MHz
  • 0-Delay Mode
  • Three Default Clock Outputs at Power Up
  • Multi-mode: Dual PLL, Single PLL, and Clock Distribution
  • Industrial Temperature Range: -40 to 85 °C
  • 3.15 V to 3.45 V Operation
  • Package: 64-Pin WQFN (9.0 x 9.0 x 0.8 mm)

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Parametrics Compare all products in Dual / Cascaded PLL

 
Input Level
Output Level
Output Frequency (Min) (MHz)
Output Frequency (Max) (MHz)
No. of Outputs
Divider Ratio
Operating Temperature Range (C)
Supply Voltage (Min) (V)
Supply Voltage (Max) (V)
VCO Frequency (Min) (MHz)
VCO Frequency (Max) (MHz)
Pin/Package
RMS Jitter
Approx. Price (US$)
Special Features
LMK04906 LMK04803 LMK04805 LMK04806 LMK04808
LVCMOS
LVDS
LVPECL    
LVPECL     LVPECL     LVPECL     LVPECL    
LVCMOS     LVCMOS     LVCMOS     LVCMOS     LVCMOS    
0.22     0.22     0.22     0.22     0.22    
2600     2030     2370     2600     3072    
6     14     14     14     14    
1 to 1045     1 to 1045     1 to 1045     1 to 1045     1 to 1045    
-40 to 85     -40 to 85     -40 to 85     -40 to 85     -40 to 85    
3.15     3.15     3.15     3.15     3.15    
3.45     3.45     3.45     3.45     3.45    
2370     1840     2148     2370     2750    
2600     2030     2370     2600     3072    
64WQFN     64WQFN     64WQFN     64WQFN     64WQFN    
0.1     0.111     0.111     0.111     0.111    
6.49 | 1ku     8.70 | 1ku     8.70 | 1ku     8.70 | 1ku     8.70 | 1ku    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    
3.3V Vcc/Vdd
Multiplier/Divider    
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