SBASB89 May   2025 ADS117L14 , ADS117L18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Idle and Standby Modes
      3. 7.4.3 Power-Down
      4. 7.4.4 Speed Modes
      5. 7.4.5 Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6 Conversion-Start Delay Time
      7. 7.4.7 Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8 Diagnostics
        1. 7.4.8.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.8.2 SPI CRC
        3. 7.4.8.3 Register Map CRC
        4. 7.4.8.4 ADC Error
        5. 7.4.8.5 SPI Address Range
        6. 7.4.8.6 SCLK Counter
        7. 7.4.8.7 Clock Counter
        8. 7.4.8.8 Frame-Sync CRC
        9. 7.4.8.9 Self Test
      9. 7.4.9 Frame-Sync Data Port
        1. 7.4.9.1  Data Packet
        2. 7.4.9.2  Data Format
        3. 7.4.9.3  STATUS_DP Header Byte
        4. 7.4.9.4  FSYNC Pin
        5. 7.4.9.5  DCLK Pin
        6. 7.4.9.6  DOUTx Pins
        7. 7.4.9.7  DINx Pins
        8. 7.4.9.8  Time Division Multiplexing
        9. 7.4.9.9  Daisy Chain
        10. 7.4.9.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Anti-alias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.8.2.1 Sinc4 Filter

The sinc4 filter performs averaging and decimation of the modulator data to produce data rates up to 1365.3kSPS in max-speed mode, 1066.6kSPS in high-speed mode, 533.3kSPS in mid-speed mode and 133.333kSPS in low-speed mode. Increasing the OSR value decreases the ADC data rate that reduces signal bandwidth and total noise resulting from increased data averaging and decimation.

Table 7-19 lists the sinc4 filter characteristics.

Table 7-3 Sinc4 Filter Characteristics
MODEfCLK
(MHz)		OSR DATA RATE
(kSPS)		–3dB FREQUENCY
(kHz)		LATENCY TIME
(μs)(1)
Max speed32.768121365.3310.23.9
High speed25.61066.6242.35.1
Mid speed12.8533.3
121.210.1
Low speed3.2133.3330.340.5
Max speed32.768161024232.74.9
High speed25.6800181.86.3
Mid speed12.840090.912.6
Low speed3.210022.750.5
Max speed32.76824682.67155.16.9
High speed25.6533.3121.28.9
Mid speed12.8266.6760.617.1
Low speed3.266.6715.170.8
Max speed32.76832512116.38.9
High speed25.640090.911.4
Mid speed12.820045.422.8
Low speed3.25011.491.4
Max speed32.7686425658.216.6
High speed25.620045.421.3
Mid speed12.810022.742.6
Low speed3.2255.68171
Max speed32.76812812829.132.3
High speed25.610022.741.3
Mid speed12.85011.482.6
Low speed3.212.52.84331
Max speed32.7682566414.563.6
High speed25.65011.481.4
Mid speed12.8255.68163
Low speed3.26.251.42651
Max speed32.768512327.27126
High speed25.6255.68162
Mid speed12.812.52.84324
Low speed3.23.1250.7101294
Max speed32.7681024163.64251
High speed25.612.52.84321
Mid speed12.86.251.42643
Low speed3.21.56250.3552570
Max speed32.768204881.82501
High speed25.66.251.42641
Mid speed12.83.1250.7101282
Low speed3.20.78130.1785130
Max speed32.768409640.9091001
High speed25.63.1250.7101281
Mid speed12.81.5630.3552562
Low speed3.20.3910.08910250
(1) Latency time increases by 8 / fCLK (µs) when the analog input buffers are enabled.

Figure 7-18 and Figure 7-19 show the sinc4 frequency response for OSR = 32. The frequency response consists of a series of response nulls occurring at multiples of fDATA with a series of decaying peaks in between. At the null frequencies, the filter has zero gain. A folded image of the filter response appears when fIN/fDATA > OSR/2, as illustrated in the frequency plot of Figure 7-19 for OSR = 32. 0dB attenuation occurs at input frequencies near n × fMOD (n = 1, 2, 3, and so on). If signals are present at these frequencies, the signal is aliased to the pass band.

ADS117L14 ADS117L18 Sinc4 Frequency Response (OSR = 32)Figure 7-18 Sinc4 Frequency Response
(OSR = 32)
ADS117L14 ADS117L18 Sinc4 Frequency Response to fMOD (OSR = 32)Figure 7-19 Sinc4 Frequency Response to fMOD (OSR = 32)