SBASB89 May   2025 ADS117L14 , ADS117L18

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Timing Diagrams
    9. 5.9 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1  Offset Error Measurement
    2. 6.2  Offset Drift Measurement
    3. 6.3  Gain Error Measurement
    4. 6.4  Gain Drift Measurement
    5. 6.5  NMRR Measurement
    6. 6.6  CMRR Measurement
    7. 6.7  PSRR Measurement
    8. 6.8  SNR Measurement
    9. 6.9  INL Error Measurement
    10. 6.10 THD Measurement
    11. 6.11 IMD Measurement
    12. 6.12 SFDR Measurement
    13. 6.13 Noise Performance
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Inputs (AINP, AINN)
        1. 7.3.1.1 Input Range
      2. 7.3.2 Reference Voltage (REFP, REFN)
        1. 7.3.2.1 Reference Voltage Range
      3. 7.3.3 Clock Operation
        1. 7.3.3.1 Clock Dividers
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 External Clock
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 VCM Output Voltage
      6. 7.3.6 GPIO
      7. 7.3.7 Modulator
      8. 7.3.8 Digital Filter
        1. 7.3.8.1 Wideband Filter
        2. 7.3.8.2 Low-Latency Filter (Sinc)
          1. 7.3.8.2.1 Sinc4 Filter
          2. 7.3.8.2.2 Sinc4 + Sinc1 Cascade Filter
          3. 7.3.8.2.3 Sinc3 Filter
          4. 7.3.8.2.4 Sinc3 + Sinc1 Filter
    4. 7.4 Device Functional Modes
      1. 7.4.1 Reset
        1. 7.4.1.1 RESET Pin
        2. 7.4.1.2 Reset by SPI Register
        3. 7.4.1.3 Reset by SPI Input Pattern
      2. 7.4.2 Idle and Standby Modes
      3. 7.4.3 Power-Down
      4. 7.4.4 Speed Modes
      5. 7.4.5 Synchronization
        1. 7.4.5.1 Synchronized Control Mode
        2. 7.4.5.2 Start/Stop Control Mode
      6. 7.4.6 Conversion-Start Delay Time
      7. 7.4.7 Calibration
        1. 7.4.7.1 Offset Calibration Registers
        2. 7.4.7.2 Gain Calibration Registers
        3. 7.4.7.3 Calibration Procedure
      8. 7.4.8 Diagnostics
        1. 7.4.8.1 ERROR Pin and ERR_FLAG Bit
        2. 7.4.8.2 SPI CRC
        3. 7.4.8.3 Register Map CRC
        4. 7.4.8.4 ADC Error
        5. 7.4.8.5 SPI Address Range
        6. 7.4.8.6 SCLK Counter
        7. 7.4.8.7 Clock Counter
        8. 7.4.8.8 Frame-Sync CRC
        9. 7.4.8.9 Self Test
      9. 7.4.9 Frame-Sync Data Port
        1. 7.4.9.1  Data Packet
        2. 7.4.9.2  Data Format
        3. 7.4.9.3  STATUS_DP Header Byte
        4. 7.4.9.4  FSYNC Pin
        5. 7.4.9.5  DCLK Pin
        6. 7.4.9.6  DOUTx Pins
        7. 7.4.9.7  DINx Pins
        8. 7.4.9.8  Time Division Multiplexing
        9. 7.4.9.9  Daisy Chain
        10. 7.4.9.10 DOUTx Timing
    5. 7.5 Programming
      1. 7.5.1 Hardware Programming
      2. 7.5.2 SPI Programming
        1. 7.5.2.1 Chip Select (CS)
        2. 7.5.2.2 Serial Clock (SCLK)
        3. 7.5.2.3 Serial Data Input (SDI)
        4. 7.5.2.4 Serial Data Output (SDO)
      3. 7.5.3 SPI Frame
      4. 7.5.4 Commands
        1. 7.5.4.1 Write Register Command
        2. 7.5.4.2 Read Register Command
      5. 7.5.5 SPI Daisy-Chain
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Input Driver
      2. 9.1.2 Anti-alias Filter
      3. 9.1.3 Reference Voltage
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD1 and AVSS
      2. 9.3.2 AVDD2
      3. 9.3.3 IOVDD
      4. 9.3.4 CAPA and CAPD
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

ADS117L14 ADS117L18 ADS117L14 RSH Package,56-Pin VQFN(Top View)Figure 4-1 ADS117L14 RSH Package,56-Pin VQFN(Top View)
ADS117L14 ADS117L18 ADS117L18 RSH Package,56-Pin VQFN(Top View)Figure 4-2 ADS117L18 RSH Package,56-Pin VQFN(Top View)
Table 4-1 Pin Functions
NAMEADS117L14 PINADS117L18 PINTYPE(1)DESCRIPTION
AINN04444IChannel 0 negative analog input. See the Analog Inputs section for details.
AINN14242IChannel 1 negative analog input. See the Analog Inputs section for details.
AINN24040IChannel 2 negative analog input. See the Analog Inputs section for details.
AINN33838IChannel 3 negative analog input. See the Analog Inputs section for details.
AINN4–-36IChannel 4 negative analog input. See the Analog Inputs section for details.
AINN5–-34IChannel 5 negative analog input. See the Analog Inputs section for details.
AINN6–-32IChannel 6 negative analog input. See the Analog Inputs section for details.
AINN7–-30IChannel 7 negative analog input. See the Analog Inputs section for details.
AINP04343IChannel 0 positive analog input. See the Analog Inputs section for details.
AINP14141IChannel 1 positive analog input. See the Analog Inputs section for details.
AINP23939IChannel 2 positive analog input. See the Analog Inputs section for details.
AINP33737IChannel 3 positive analog input. See the Analog Inputs section for details.
AINP4–-35IChannel 4 positive analog input. See the Analog Inputs section for details.
AINP5–-33IChannel 5 positive analog input. See the Analog Inputs section for details.
AINP6–-31IChannel 6 positive analog input. See the Analog Inputs section for details.
AINP7–-29IChannel 7 positive analog input. See the Analog Inputs section for details.
AVDD123, 2423, 24PPositive analog supply 1. See the Power Supply Recommendations section for details.
AVDD22525PPositive analog supply 2. See the Power Supply Recommendations section for details.
AVSS22, 28, 29, 30, 31, 32, 33, 34, 35, 36, 45, 5122, 28, 45, 51PNegative analog supply. See the Power Supply Recommendations section for details.
CAPA26, 2726, 27PAnalog voltage regulator output bypass. See the CAPA and CAPD section for details.
CAPD2020PDigital voltage regulator output bypass. See the CAPA and CAPD section for details.
CLKIN1616IClock input. See the Clock Operation section for details.
CS/SPEED5555ISPI mode: Active-low chip select. See the SPI Programming section for details.
Hardware mode (tri-state input): Speed range select.
See the Hardware Programming section for details.
DCLK1414OFrame-sync bit clock output. See the Frame-Sync Data Port section for details.
DGND17, 2117, 21GNDDigital ground.
DIN0/GPIO713–-I/ODaisy-chain data input 0. See the Frame-Sync Data Port section for details.
General-purpose input-output 7. See the GPIO section for details.
DIN1/GPIO612–-I/ODaisy-chain data input 1. See the Frame-Sync Data Port section for details.
General-purpose input-output 6. See the GPIO section for details.
DOUT066OData output 0. See the Frame-Sync Data Port section for details.
DOUT177OData output 1. See the Frame-Sync Data Port section for details.
DOUT2/GPIO288I/OData output 2. See the Frame-Sync Data Port section for details.
General-purpose input-output 2. See the GPIO section for details.
DOUT3/GPIO399I/OData output 3. See the Frame-Sync Data Port section for details.
General-purpose input-output 3. See the GPIO section for details.
DOUT4/DIN3/GPIO4–-10I/OData output 4 and daisy-chain data input 3. See the Frame-Sync Data Port section for details.
General-purpose input-output 4. See the GPIO section for details.
DOUT5/DIN2/GPIO5–-11I/OData output 5 and daisy-chain data input 2. See the Frame-Sync Data Port section for details.
General-purpose input-output 5. See the GPIO section for details.
DOUT6/DIN1/GPIO6–-12I/OData output 6 and daisy-chain data input 1. See the Frame-Sync Data Port section for details.
General-purpose input-output 6. See the GPIO section for details.
DOUT7/DIN0/GPIO7–-13I/OData output 7 and daisy-chain data input 0. See the Frame-Sync Data Port section for details.
General-purpose input-output 7. See the GPIO section for details.
ERROR55OOpen-drain output error signal. See the ERROR Pin and ERR_FLAG Bit section for details.
FSYNC1515OFrame-sync word clock output. See the Frame-Sync Data Port section for details.
GPIO0/TDM33I/OGeneral purpose input-output 0. See the GPIO section for details.
Hardware mode (tri-state input): TDM ratio select.
See the Hardware Programming section for details.
GPIO1/HDR44I/OGeneral purpose input-output 1. See the GPIO section for details.
Hardware mode (tri-state input): Data header select.
See the Hardware Programming section for details.
GPIO410–-I/OGeneral-purpose input-output 4. See the GPIO section for details.
GPIO511–-I/OGeneral-purpose input-output 5. See the GPIO section for details.
IOVDD18, 1918, 19PDigital I/O supply voltage. See the Power Supply Recommendations section for details.
MODE5454ITri-state input. Configuration mode select:
1 = SPI program mode
0 or float = Hardware program mode
REFN47, 4847, 48INegative reference voltage input. See the Reference Voltage section for details.
REFP49, 5049, 50IPositive reference voltage input. See the Reference Voltage section for details.
RESET5252IReset input, active low. See the RESET Pin section for details.
SCLK/FLTR5656ISPI mode: Serial clock input. See the SPI Programming section for details.
Hardware mode (tri-state input): Filter mode select.
See the Hardware Programming section for details.
SDI/OSR011ISPI mode: Serial data input. See the SPI Programming section for details.
Hardware mode (tri-state input): Filter OSR0 select.
See the Hardware Programming section for details.
SDO/OSR122I/OSPI mode: Serial data output. See the SPI Programming section for details.
Hardware mode (tri-state input): Filter OSR1 select.
See the Hardware Programming section for details.
START5353IConversion control. See the Synchronization section for details.
VCM4646OCommon-mode voltage output. See the VCM Output Voltage section for details.
Thermal Pad—Thermal power pad. Connect thermal pad to AVSS.
(1) I = input, O = output, I/O = bidirectional input-output, P = power, GND = ground.