SPRSP35F February   2019  – January 2021 DRA829J

ADVANCE INFORMATION  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1. 3.1 Functional Block Diagram
  4. 4 Revision History
  5. 5 Device Comparison
    1. 5.1 Related Products
  6. 6 Terminal Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1  ADC
        1. 6.3.1.1 MCU Domain
      2. 6.3.2  DDRSS
        1. 6.3.2.1 MAIN Domain
      3. 6.3.3  GPIO
        1. 6.3.3.1 MAIN Domain
        2. 6.3.3.2 WKUP Domain
      4. 6.3.4  I2C
        1. 6.3.4.1 MAIN Domain
        2. 6.3.4.2 MCU Domain
        3. 6.3.4.3 WKUP Domain
      5. 6.3.5  I3C
        1. 6.3.5.1 MAIN Domain
        2. 6.3.5.2 MCU Domain
      6. 6.3.6  MCAN
        1. 6.3.6.1 MAIN Domain
        2. 6.3.6.2 MCU Domain
      7. 6.3.7  MCSPI
        1. 6.3.7.1 MAIN Domain
        2. 6.3.7.2 MCU Domain
      8. 6.3.8  UART
        1. 6.3.8.1 MAIN Domain
        2. 6.3.8.2 MCU Domain
        3. 6.3.8.3 WKUP Domain
      9. 6.3.9  MDIO
        1. 6.3.9.1 MCU Domain
      10. 6.3.10 CPSW2G
        1. 6.3.10.1 MCU Domain
      11. 6.3.11 CPSW9G
        1. 6.3.11.1 MAIN Domain
      12. 6.3.12 ECAP
        1. 6.3.12.1 MAIN Domain
      13. 6.3.13 EQEP
        1. 6.3.13.1 MAIN Domain
      14. 6.3.14 EHRPWM
        1. 6.3.14.1 MAIN Domain
      15. 6.3.15 USB
        1. 6.3.15.1 MAIN Domain
      16. 6.3.16 SERDES
        1. 6.3.16.1 MAIN Domain
      17. 6.3.17 OSPI
        1. 6.3.17.1 MCU Domain
      18. 6.3.18 Hyperbus
        1. 6.3.18.1 MCU Domain
      19. 6.3.19 GPMC
        1. 6.3.19.1 MAIN Domain
      20. 6.3.20 MMC
        1. 6.3.20.1 MAIN Domain
      21. 6.3.21 CPTS
        1. 6.3.21.1 MAIN Domain
      22. 6.3.22 UFS
        1. 6.3.22.1 MAIN Domain
      23. 6.3.23 PRU_ICSSG
        1. 6.3.23.1 MAIN Domain
      24. 6.3.24 MCASP
        1. 6.3.24.1 MAIN Domain
      25. 6.3.25 DSS
        1. 6.3.25.1 MAIN Domain
      26. 6.3.26 DP
        1. 6.3.26.1 MAIN Domain
      27. 6.3.27 Camera Adaptor Layer (CAL) Subsystem
        1. 6.3.27.1 MAIN Domain
      28. 6.3.28 DSI_TX
        1. 6.3.28.1 MAIN Domain
      29. 6.3.29 VPFE
        1. 6.3.29.1 MAIN Domain
      30. 6.3.30 DMTIMER
        1. 6.3.30.1 MAIN Domain
        2. 6.3.30.2 MCU Domain
      31. 6.3.31 Emulation and Debug
        1. 6.3.31.1 MAIN Domain
      32. 6.3.32 System and Miscellaneous
        1. 6.3.32.1 Boot Mode Configuration
          1. 6.3.32.1.1 MAIN Domain
          2. 6.3.32.1.2 MCU Domain
        2. 6.3.32.2 Clock
          1. 6.3.32.2.1 MAIN Domain
          2. 6.3.32.2.2 WKUP Domain
        3. 6.3.32.3 System
          1. 6.3.32.3.1 MAIN Domain
          2. 6.3.32.3.2 WKUP Domain
        4. 6.3.32.4 EFUSE
      33. 6.3.33 Power Supply
    4. 6.4 Pin Multiplexing
    5. 6.5 Connections for Unused Pins
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On-Hour (POH) Limits
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 USB2PHY Electrical Characteristics
      2. 7.7.2 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics
      3. 7.7.3 UFS M-PHY Electrical Characteristics
      4. 7.7.4 eDP/DP AUX-PHY Electrical Characteristics
      5. 7.7.5 DDR0 Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics for ALF Package
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Sequencing
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Combined MCU and Main Domains Power-Up Sequencing
        3. 7.10.2.3 Combined MCU and Main Domains Power- Down Sequencing
        4. 7.10.2.4 Independent MCU and Main Domains Power- Up Sequencing
        5. 7.10.2.5 Independent MCU and Main Domains, Primary Power- Down Sequencing
        6. 7.10.2.6 Entry and Exit of MCU Only State
        7. 7.10.2.7 Entry and Exit of DDR Retention State
      3. 7.10.3 Reset Timing
        1. 7.10.3.1 Reset Electrical Data/Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input and Output Clocks / Oscillators
          1. 7.10.4.1.1 WKUP_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 WKUP_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 Auxiliary OSC1 Internal Oscillator Clock Source
            1. 7.10.4.1.3.1 Load Capacitance
            2. 7.10.4.1.3.2 Shunt Capacitance
          4. 7.10.4.1.4 Auxiliary OSC1 LVCMOS Digital Clock Source
          5. 7.10.4.1.5 Auxiliary OSC1 Not Used
          6. 7.10.4.1.6 WKUP_LFOSC0 Internal Oscillator Clock Source
          7. 7.10.4.1.7 WKUP_LFOSC0 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
        4. 7.10.4.4 Device Inputs and Outputs Module Clocks Frequencies
      5. 7.10.5 Peripherals
        1. 7.10.5.1  ATL
          1. 7.10.5.1.1 Switching Characteristics Over Recommended Operating Conditions for ATL_CLK[x]
          2. 7.10.5.1.2 Timing Requirements for ATL_AWS[x]
          3. 7.10.5.1.3 Timing Requirements for ATL_BWS[x]
          4. 7.10.5.1.4 Switching Characteristics Over Recommended Operating Conditions for ATCLKOUT[x]
        2. 7.10.5.2  VPFE
        3. 7.10.5.3  CPSW2G
          1. 7.10.5.3.1 CPSW2G MDIO Interface Timings
          2. 7.10.5.3.2 CPSW2G RMII Timings
            1. 7.10.5.3.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.10.5.3.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.10.5.3.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 7.10.5.3.3 CPSW2G RGMII Timings
            1. 7.10.5.3.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.10.5.3.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.3.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.10.5.3.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL – RGMII Mode
        4. 7.10.5.4  CPSW9G
          1. 7.10.5.4.1 CPSW9G MDIO Interface Timings
          2. 7.10.5.4.2 CPSW9G RMII Timings
            1. 7.10.5.4.2.1 Timing Requirements for RMII[x]_REFCLK – RMII Mode
            2. 7.10.5.4.2.2 Timing Requirements for RMII[x]_RXD[1:0], RMII[x]_CRS_DV, and RMII[x]_RXER – RMII Mode
            3. 7.10.5.4.2.3 Switching Characteristics for RMII[x]_TXD[1:0], and RMII[x]_TXEN – RMII Mode
          3. 7.10.5.4.3 CPSW9G RGMII Timings
            1. 7.10.5.4.3.1 Timing Requirements for RGMII[x]_RCLK – RGMII Mode
            2. 7.10.5.4.3.2 Timing Requirements for RGMII[x]_RD[3:0], and RGMII[x]_RCTL – RGMII Mode
            3. 7.10.5.4.3.3 Switching Characteristics for RGMII[x]_TCLK – RGMII Mode
            4. 7.10.5.4.3.4 Switching Characteristics for RGMII[x]_TD[3:0], and RGMII[x]_TX_CTL – RGMII Mode
        5. 7.10.5.5  CSI2
          1. 7.10.5.5.1 CSI-2 MIPI D-PHY
        6. 7.10.5.6  DDRSS
        7. 7.10.5.7  DSS
        8. 7.10.5.8  eCAP
          1. 7.10.5.8.1 Timing Requirements for eCAP
          2. 7.10.5.8.2 Switching Characteristics for eCAP
        9. 7.10.5.9  EPWM
          1. 7.10.5.9.1 Timing Requirements for eHRPWM
          2. 7.10.5.9.2 Switching Characteristics for eHRPWM
        10. 7.10.5.10 eQEP
          1. 7.10.5.10.1 Timing Requirements for eQEP
          2. 7.10.5.10.2 Switching Characteristics for eQEP
        11. 7.10.5.11 GPIO
          1. 7.10.5.11.1 GPIO Timing Requirements
          2. 7.10.5.11.2 GPIO Switching Characteristics
        12. 7.10.5.12 GPMC
          1. 7.10.5.12.1 GPMC and NOR Flash — Synchronous Mode
            1. 7.10.5.12.1.1 GPMC and NOR Flash Timing Requirements — Synchronous Mode
            2. 7.10.5.12.1.2 GPMC and NOR Flash Switching Characteristics – Synchronous Mode
          2. 7.10.5.12.2 GPMC and NOR Flash — Asynchronous Mode
            1. 7.10.5.12.2.1 GPMC and NOR Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.2.2 GPMC and NOR Flash Switching Characteristics – Asynchronous Mode
          3. 7.10.5.12.3 GPMC and NAND Flash — Asynchronous Mode
            1. 7.10.5.12.3.1 GPMC and NAND Flash Timing Requirements – Asynchronous Mode
            2. 7.10.5.12.3.2 GPMC and NAND Flash Switching Characteristics – Asynchronous Mode
        13. 7.10.5.13 HyperBus
          1. 7.10.5.13.1 Timing Requirements for HyperBus Initialization
          2. 7.10.5.13.2 HyperBus 166 MHz Switching Characteristics
          3. 7.10.5.13.3 HyperBus 100 MHz Switching Characteristics
        14. 7.10.5.14 I2C
          1. 7.10.5.14.1 Timing Requirements for I2C Input Timings
        15. 7.10.5.15 I3C
        16. 7.10.5.16 MCAN
        17. 7.10.5.17 MCASP
          1. 7.10.5.17.1 Timing Requirements for MCASP
        18. 7.10.5.18 MCSPI
          1. 7.10.5.18.1 MCSPI — Master Mode
            1. 7.10.5.18.1.1 Timing Requirements for SPI – Master Mode
          2. 7.10.5.18.2 MCSPI — Slave Mode
            1. 7.10.5.18.2.1 Timing Requirements for SPI – Slave Mode
        19. 7.10.5.19 NAVSS
          1. 7.10.5.19.1 Timing Requirements for CPTS Input
          2. 7.10.5.19.2 Switching Characteristics for CPTS Output
        20. 7.10.5.20 OSPI
          1. 7.10.5.20.1 OSPI With Data Training
            1. 7.10.5.20.1.1 OSPI Switching Characteristics – Data Training
          2. 7.10.5.20.2 OSPI Without Data Training
            1. 7.10.5.20.2.1 OSPI Switching Characteristics – DDR Mode
            2. 7.10.5.20.2.2 OSPI Switching Characteristics – SDR Mode
            3. 7.10.5.20.2.3 OSPI Timing Requirements – DDR Mode
            4. 7.10.5.20.2.4 OSPI Timing Requirements – SDR Mode
        21. 7.10.5.21 OLDI
          1. 7.10.5.21.1 OLDI Switching Characteristics
        22. 7.10.5.22 PCIE
        23. 7.10.5.23 Timers
          1. 7.10.5.23.1 Timing Requirements for Timers
          2. 7.10.5.23.2 Switching Characteristics for Timers
        24. 7.10.5.24 UART
          1. 7.10.5.24.1 Timing Requirements for UART
          2. 7.10.5.24.2 Switching Characteristics Over Recommended Operating Conditions for UART
        25. 7.10.5.25 USB
      6. 7.10.6 Emulation and Debug
        1. 7.10.6.1 Debug Trace
        2. 7.10.6.2 IEEE 1149.1 Standard–Test–Access Port (JTAG)
          1. 7.10.6.2.1 JTAG Electrical Data and Timing
            1. 7.10.6.2.1.1 Timing Requirements for IEEE 1149.1 JTAG
            2. 7.10.6.2.1.2 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A72
      2. 8.2.2 Arm Cortex-R5F
      3. 8.2.3 DSP C71x
      4. 8.2.4 DSP C66x
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 PRU_ICSSG
        1. 8.3.1.1 PRU_ICSSG PRU Cores
        2. 8.3.1.2 PRU_ICSSG Broadside Accelerators
        3. 8.3.1.3 PRU_ICSSG Local INTC
        4. 8.3.1.4 PRU_ICSSG UART Module
        5. 8.3.1.5 PRU_ICSSG ECAP Module
        6. 8.3.1.6 PRU_ICSSG PWM Module
        7. 8.3.1.7 PRU_ICSSG MII_G_RT Module
        8. 8.3.1.8 PRU_ICSSG MII MDIO Module
        9. 8.3.1.9 PRU_ICSSG IEP
      2. 8.3.2 GPU
      3. 8.3.3 D5520MP2
      4. 8.3.4 VXE384MP2
    4. 8.4 Other Subsystems
      1. 8.4.1 MSMC
      2. 8.4.2 NAVSS
        1. 8.4.2.1 NAVSS0
        2. 8.4.2.2 MCU_NAVSS
        3. 8.4.2.3
      3. 8.4.3 PDMA Controller
      4. 8.4.4 Peripherals
        1. 8.4.4.1  ADC
        2. 8.4.4.2  ATL
        3. 8.4.4.3  AASRC
        4. 8.4.4.4  CSI
          1. 8.4.4.4.1 Camera Streaming Interface Receiver (CSI_RX_IF) and MIPI DPHY Receiver (DPHY_RX)
          2. 8.4.4.4.2 Camera Streaming Interface Transmitter (CSI_TX_IF)
        5. 8.4.4.5  CPSW2G
        6. 8.4.4.6  CPSW9G
        7. 8.4.4.7  DCC
        8. 8.4.4.8  DDRSS
        9. 8.4.4.9  DSS
          1. 8.4.4.9.1 DSI
          2. 8.4.4.9.2 eDP
        10. 8.4.4.10 VPFE
        11. 8.4.4.11 eCAP
        12. 8.4.4.12 EPWM
        13. 8.4.4.13 ELM
        14. 8.4.4.14 ESM
        15. 8.4.4.15 eQEP
        16. 8.4.4.16 GPIO
        17. 8.4.4.17 GPMC
        18. 8.4.4.18 Hyperbus
        19. 8.4.4.19 I2C
        20. 8.4.4.20 I3C
        21. 8.4.4.21 MCAN
        22. 8.4.4.22 MCASP
        23. 8.4.4.23 MCRC Controller
        24. 8.4.4.24 MCSPI
        25. 8.4.4.25 MMC/SD
        26. 8.4.4.26 OSPI
        27. 8.4.4.27 PCIE
        28. 8.4.4.28 SerDes
        29. 8.4.4.29 WWDT
        30. 8.4.4.30 Timers
        31. 8.4.4.31 UART
        32. 8.4.4.32 USB
        33. 8.4.4.33 UFS
  9. 9 Applications and Implementation
    1. 9.1 Power Supply Mapping
    2. 9.2 Device Connection and Layout Fundamentals
      1. 9.2.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.2.1.1 Power Distribution Network Implementation Guidance
      2. 9.2.2 External Oscillator
      3. 9.2.3 JTAG and EMU
      4. 9.2.4 Reset
      5. 9.2.5 Unused Pins
      6. 9.2.6 Hardware Design Guide for AM752x/DRA829/TDA4VM Devices
    3. 9.3 Peripheral- and Interface-Specific Design Information
      1. 9.3.1 LPDDR4 Board Design and Layout Guidelines
      2. 9.3.2 OSPI and QSPI Board Design and Layout Guidelines
        1. 9.3.2.1 No Loopback and Internal Pad Loopback
        2. 9.3.2.2 External Board Loopback
        3. 9.3.2.3 DQS (only available in Octal Flash devices)
      3. 9.3.3 SERDES REFCLK Design Guidelines
      4. 9.3.4 USB VBUS Design Guidelines
      5. 9.3.5 System Power Supply Monitor Design Guidelines
      6. 9.3.6 High Speed Differential Signal Routing Guidance
      7. 9.3.7 External Capacitors
      8. 9.3.8 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ALF|827
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

Processor cores:

  • Dual 64-bit Arm®Cortex®-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB shared L2 cache per dual-core Arm®Cortex®-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per Cortex®-A72 Core
  • Six Arm®Cortex®-R5F MCUs at up to 1.0 GHz, 8K DMIPS
    • 16K I-Cache, 16K D-Cache, 64K L2 TCM
    • Two Arm®Cortex®-R5F MCUs in isolated MCU subsystem
    • Four Arm®Cortex®-R5F MCUs in general compute partition
  • Deep-learning Matrix Multiply Accelerator (MMA), up to 8 TOPS (8b) at 1.0 GHz
  • C7x floating point, vector DSP, up to 1.0 GHz,
    80 GFLOPS, 256 GOPS
  • Two C66x floating point DSP, up to 1.35 GHz,
    40 GFLOPS, 160 GOPS
  • 3D GPU PowerVR® Rogue 8XE GE8430, up to 750 MHz, 96 GFLOPS, 6 Gpix/sec

    Memory subsystem:

  • 2MB of on-chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types
    • Supports speeds up to 4266 MT/s
    • 32-bit data bus with inline ECC up to 14.9GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Display subsystem:

  • One eDP/DP interface with Multi-Display Support (MST)
    • HDCP1.4/HDCP2.2 high-bandwidth digital content protection
  • One DSI TX (up to 2.5K)
  • Up to two DPI

    Video acceleration:

  • Ultra-HD video, one (3840 × 2160p, 60 fps), or two (3840 × 2160p, 30 fps) H.264/H.265 decode
  • Full-HD video, four (1920 × 1080p, 60 fps), or eight (1920 × 1080p, 30 fps) H.264/H.265 decode
  • Full-HD video, one (1920 × 1080p, 60 fps), or up to three (1920 × 1080p, 30 fps) H.264 encode

    Functional Safety:

  • Functional Safety-Compliant targeted
    • Developed for functional safety applications
    • Documentation available to aid ISO 26262 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for Main Domain
    • Safety-related certification
      • ISO 26262 planned

  • Device security:

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    High speed serial interfaces:

  • Two CSI2.0 4L RX plus one CSI2.0 4L TX
  • Integrated ethernet switch supporting
    (total of 8 external ports)
    • Up to eight 2.5Gb SGMII
    • Up to eight RMII (10/100) or RGMII (10/100/1000)
    • Up to two QSGMII
  • Up to four PCI-Express® (PCIe) Gen3 controllers
    • Gen1 (2.5GT/s), Gen2 (5.0GT/s), and Gen3 (8.0GT/s) operation with auto-negotiation
    • Up to two lanes per controller
  • Two USB 3.0 dual-role device (DRD) subsystem
    • Two enhanced SuperSpeed Gen1 ports
    • Each port supports Type-C switching
    • Each port independently configurable as USB host, USB peripheral, or USB DRD

    Automotive interfaces:

  • Sixteen Modular Controller Area Network (MCAN) modules with full CAN-FD support

    Audio interfaces:

  • Twelve Multichannel Audio Serial Port (MCASP) modules

    Flash memory interfaces:

  • Embedded MultiMediaCard interface ( eMMC™ 5.1)
  • Universal Flash Storage (UFS 2.1) interface with two lanes
  • Two Secure Digital® 3.0/Secure Digital Input Output 3.0 interfaces (SD3.0/SDIO3.0)
  • Two simultaneous flash interfaces configured as
    • One OSPI and one QSPI flash interfaces
    • or HyperBus™ and QSPI flash interface

    System-on-Chip (SoC) architecture:

  • 16-nm FinFET technology
  • 24 mm × 24 mm, 0.8-mm pitch, 827-pin FCBGA (ALF), enables IPC class 3 PCB routing

    TPS6594-Q1 Companion Power Management ICs (PMIC):

  • Functional Safety support up to ASIL-D
  • Flexible mapping to support different use cases