SPRSP35J February 2019 – August 2021 DRA829J , DRA829V
Refer to the PDF data sheet for device specific package drawings
For more details about features and additional description information on the device LPDDR4 Memory Interfaces, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
The device has dedicated interface to LPDDR4. It supports JEDEC JESD209-4B standard compliant LPDDR4 SDRAM devices with the following features:
Table 7-40 and Figure 7-53 present switching characteristics for DDRSS.
|1||tc(DDR_CKP/DDR_CKN)||Cycle time, DDR0_CKP and DDR0_CKN||LPDDR4||0.536||3.003||ns|
For more information, see DDR Subsystem (DDRSS) section in Memory Controllers chapter in the device TRM.