SPRSP35J February 2019 – August 2021 DRA829J , DRA829V
Refer to the PDF data sheet for device specific package drawings
This section describes the Unused/Reserved balls connection requirements.
All VMON and power balls must be supplied with the voltages specified in Section 7.4, Recommended Operating Conditions, unless otherwise specified in Section 6.3, Signal Descriptions.
MMC1_SDCD and MMC2_SDCD must be pulled down for respective MMC modules to work properly.
|BALL NUMBER||BALL NAME||CONNECTION REQUIREMENTS|
|M29||WKUP_OSC0_XI||Each of these balls must be connected to VSS through a separate external pull resistor to ensure these balls are held to a valid logic low level if unused.|
|AE18||SERDES0_REXT||Each of these balls must be connected to VSS through appropriate external pull resistor to ensure these balls are held to a valid logic low level if unused. The resistor value for the SERDES[4:0]_REXT pins is 3.01 kΩ ±1%, for the CSI[1:0]_RXRCALIB, USB[1:0]_RCALIB, and DSI_TXRCALIB pins is 500 Ω ±1%. This is the same connection as during functional mode.|
|D28||MCU_RESETz||Each of these balls must be connected to the corresponding power supply through a separate external pull resistor to ensure these balls are held to a valid logic high level if unused.(1)|
|AB11||VPP_CORE||Each of these balls must be left unconnected if unused.|
|A29 / AJ1 / U11 / U12 / U13 / T11 / T12 / T13 / M11 / M12 / M13 / N11 / N12 / N13||These balls do not exist on the package.|
|N25 / AJ29 / P26 / R27 / AD4 / E18 / F18 / G10 / F11 / N6 / L6 / F6 / E6 / G9 / F10 / AA23 / F13||These balls must be left unconnected.|
All other unused signal balls without Pad Configuration Register can be left unconnected.
All other unused signal balls with a Pad Configuration Register can be left unconnected with their multiplexing mode set to GPIO input and internal pulldown resistor enabled.
Unused balls are defined as those which only connect to a PCB solder pad. This is the only use case where internal pull resistors are allowed as the only source/sink to hold a valid logic level.
Any balls connected to a via, test point, or PCB trace are considered used and must not depend on the internal pull resistor to hold a valid logic level.
Internal pull resistors are weak and may not source enough current to maintain a valid logic level for some operating conditions. This may be the case when connected to components with leakage to the opposite logic level, or when external noise sources couple to signal traces attached to balls which are only pulled to a valid logic level by the internal resistor. Therefore, external pull resistors may be required to hold a valid logic level on balls with external connections.
If balls are allowed to float between valid logic levels, the input buffer may enter a high-current state which could damage the IO cell.