SPRSP35J February 2019 – August 2021 DRA829J , DRA829V
Refer to the PDF data sheet for device specific package drawings
The crystal circuit must be designed such that it applies the appropriate capacitive load to the crystal, as defined by the crystal manufacturer. The capacitive load, CL, of this circuit is a combination of discrete capacitors CL1, CL2, and several parasitic contributions. PCB signal traces which connect crystal circuit components to OSC1_XI and OSC1_XO have parasitic capacitance to ground, CPCBXI and CPCBXO, where the PCB designer should be able to extract parasitic capacitance for each signal trace. The OSC1 circuits and device package have combined parasitic capacitance to ground, CPCBXI and CPCBXO, where these parasitic capacitance values are defined in Table 7-23.
Load capacitors, CL1 and CL2 in Figure 7-28, should be chosen such that the below equation is satisfied. CL in the equation is the load specified by the crystal manufacturer.
CL = [(CL1 + CPCBXI + CXI) × (CL2 + CPCBXO + CXO)] / [(CL1 + CPCBXI + CXI) + (CL2 + CPCBXO + CXO)]
To determine the value of CL1 and CL2, multiply the capacitive load value CL by 2. Using this result, subtract the combined values of CPCBXI + CXI to determine the value of CL1 and the combined values of CPCBXO + CXO to determine the value of CL2. For example, if CL = 10 pF, CPCBXI = 2.9 pF, CXI = 0.5 pF, CPCBXO = 3.7 pF, CXO = 0.5 pF, the value of CL1 = [(2CL) - (CPCBXI + CXI)] = [(2 × 10 pF) - 2.9 pF - 0.5 pF)] = 16.6 pF and CL2 = [(2CL) - (CPCBXO + CXO)] = [(2 × 10 pF) - 3.7 pF - 0.5 pF)] = 15.8 pF