SPRSP35J February 2019 – August 2021 DRA829J , DRA829V
Refer to the PDF data sheet for device specific package drawings
The device has ten instances of GPIO modules. The GPIO modules are integrated in three groups.
The GPIO pins are grouped into banks (16 pins per bank), which means that each GPIO module provides up to 144 dedicated general-purpose pins with input and output capabilities; thus, the general-purpose interface supports up to 432 (3 instances × (9 banks × 16 pins)) pins. Since WKUP_GPIOu_[84:143] (u = 0, 1), GPIOn_[128:143] (n = 0, 2, 4, 6), and GPIOm_[36:143] (m = 1, 3, 5 ,7) are reserved in this device, general purpose interface supports up to 248 I/O pins.
For more details about features and additional description information on the device General-Purpose Interface, see the corresponding sections within Section 6.3, Signal Descriptions and Section 8, Detailed Description.
The general-purpose input/output i (i = 0 to 1) is also referred to as GPIOi.
Table 7-47 represents GPIO timing conditions.
|SRI||Input slew rate||LVCMOS||0.75||6.6||V/ns|
|CL||Output load capacitance||LVCMOS||3||10||pF|
|CL||Output load capacitance||I2C Open Drain||3||100||pF|
Section 184.108.40.206.1 and Section 220.127.116.11.2 present timings and switching characteristics of the GPIO Interface.