SPRSP35J February 2019 – August 2021 DRA829J , DRA829V
Refer to the PDF data sheet for device specific package drawings
For more details about features and additional description information on the device Universal Asynchronous Receiver Transmitter, see the corresponding sections within , Section 6.3, Signal Descriptions and Section 8, Detailed Description.
Table 7-95 represents UART timing conditions.
|SRI||Input slew rate||0.5||5||V/ns|
|CL||Output load capacitance||1||30||pF|
|PCB CONNECTIVITY REQUIREMENTS|
|td(Trace Mismatch Delay)||Propagation delay mismatch across all traces||100||ps|
Section 126.96.36.199.1, Section 188.8.131.52.2, and Figure 7-119 present timing requirements and switching characteristics for UART interface.