SPRSP14D May 2019 – February 2021 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S
The ADC inputs should be kept below VDDA + 0.3 V during operation. If an ADC input exceeds this level, the VREF internal to the device may be disturbed, which can impact results for other ADC or DAC inputs using the same VREF.
The VREFHI pin must be kept below VDDA for the ADC and DAC to meet specified performance parameters. The VREFHI pin must be kept below VDDA + 0.3 V for functional operation. If the VREFHI pin exceeds VDDA + 0.3 V, a blocking circuit may activate, causing the interval value of VREFHI to float to 0 V internally, giving improper ADC conversion or DAC output.