SPRSP14D May   2019  – February 2021 TMS320F28384D , TMS320F28384D-Q1 , TMS320F28384S , TMS320F28384S-Q1 , TMS320F28386D , TMS320F28386D-Q1 , TMS320F28386S , TMS320F28386S-Q1 , TMS320F28388D , TMS320F28388S

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1. 6.3.1 Analog Signals
      2. 6.3.2 Digital Signals
      3. 6.3.3 Power and Ground
      4. 6.3.4 Test, JTAG, and Reset
    4. 6.4 Pins With Internal Pullup and Pulldown
    5. 6.5 Pin Multiplexing
      1. 6.5.1 GPIO Muxed Pins Table
      2. 6.5.2 Input X-BAR
      3. 6.5.3 Output X-BAR, CLB X-BAR, CLB Output X-BAR, and ePWM X-BAR
      4. 6.5.4 USB Pin Muxing
      5. 6.5.5 High-Speed SPI Pin Muxing
      6. 6.5.6 High-Speed SSI Pin Muxing
    6. 6.6 Connections for Unused Pins
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings – Commercial
    3. 7.3  ESD Ratings – Automotive
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Power Consumption Summary
      1. 7.5.1 System Current Consumption (External Supply)
      2. 7.5.2 Operating Mode Test Description
      3. 7.5.3 Current Consumption Graphs
      4. 7.5.4 Reducing Current Consumption
    6. 7.6  Electrical Characteristics
    7. 7.7  Thermal Resistance Characteristics for ZWT Package
    8. 7.8  Thermal Resistance Characteristics for PTP Package
    9. 7.9  Thermal Design Considerations
    10. 7.10 System
      1. 7.10.1 Power Sequencing
      2. 7.10.2 Reset Timing
        1. 7.10.2.1 Reset Sources
        2. 7.10.2.2 Reset Electrical Data and Timing
          1. 7.10.2.2.1 Reset (XRSn) Timing Requirements
          2. 7.10.2.2.2 Reset (XRSn) Switching Characteristics
          3. 7.10.2.2.3 Reset Timing Diagrams
      3. 7.10.3 Clock Specifications
        1. 7.10.3.1 Clock Sources
        2. 7.10.3.2 Clock Frequencies, Requirements, and Characteristics
          1. 7.10.3.2.1 Input Clock Frequency and Timing Requirements, PLL Lock Times
            1. 7.10.3.2.1.1 Input Clock Frequency
            2. 7.10.3.2.1.2 XTAL Oscillator Characteristics
            3. 7.10.3.2.1.3 X1 Timing Requirements
            4. 7.10.3.2.1.4 AUXCLKIN Timing Requirements
            5. 7.10.3.2.1.5 APLL Characteristics
          2. 7.10.3.2.2 Internal Clock Frequencies
            1. 7.10.3.2.2.1 Internal Clock Frequencies
          3. 7.10.3.2.3 Output Clock Frequency and Switching Characteristics
            1. 7.10.3.2.3.1 XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
        3. 7.10.3.3 Input Clocks
        4. 7.10.3.4 Crystal Oscillator
          1. 7.10.3.4.1 Crystal Oscillator Parameters
          2. 7.10.3.4.2 Crystal Equivalent Series Resistance (ESR) Requirements Table
          3. 7.10.3.4.3 Crystal Oscillator Electrical Characteristics
        5. 7.10.3.5 Internal Oscillators
          1. 7.10.3.5.1 INTOSC Characteristics
      4. 7.10.4 Flash Parameters
      5. 7.10.5 Emulation/JTAG
        1. 7.10.5.1 JTAG Electrical Data and Timing
          1. 7.10.5.1.1 JTAG Timing Requirements
          2. 7.10.5.1.2 JTAG Switching Characteristics
          3. 7.10.5.1.3 JTAG Timing
      6. 7.10.6 GPIO Electrical Data and Timing
        1. 7.10.6.1 GPIO - Output Timing
          1. 7.10.6.1.1 General-Purpose Output Switching Characteristics
          2. 7.10.6.1.2 General-Purpose Output Timing
        2. 7.10.6.2 GPIO - Input Timing
          1. 7.10.6.2.1 General-Purpose Input Timing Requirements
          2. 7.10.6.2.2 Sampling Mode
        3. 7.10.6.3 Sampling Window Width for Input Signals
      7. 7.10.7 Interrupts
        1. 7.10.7.1 External Interrupt (XINT) Electrical Data and Timing
          1. 7.10.7.1.1 External Interrupt Timing Requirements
          2. 7.10.7.1.2 External Interrupt Switching Characteristics
          3. 7.10.7.1.3 External Interrupt Timing
      8. 7.10.8 Low-Power Modes
        1. 7.10.8.1 Clock-Gating Low-Power Modes
        2. 7.10.8.2 Low-Power Mode Wakeup Timing
          1. 7.10.8.2.1 IDLE Mode Timing Requirements
          2. 7.10.8.2.2 IDLE Mode Switching Characteristics
          3. 7.10.8.2.3 IDLE Entry and Exit Timing Diagram
          4. 7.10.8.2.4 STANDBY Mode Timing Requirements
          5. 7.10.8.2.5 STANDBY Mode Switching Characteristics
          6. 7.10.8.2.6 STANDBY Entry and Exit Timing Diagram
      9. 7.10.9 External Memory Interface (EMIF)
        1. 7.10.9.1 Asynchronous Memory Support
        2. 7.10.9.2 Synchronous DRAM Support
        3. 7.10.9.3 EMIF Electrical Data and Timing
          1. 7.10.9.3.1 Asynchronous RAM
            1. 7.10.9.3.1.1 EMIF Asynchronous Memory Timing Requirements
            2. 7.10.9.3.1.2 EMIF Asynchronous Memory Switching Characteristics
            3. 7.10.9.3.1.3 EMIF Asynchronous Memory Timing Diagrams
          2. 7.10.9.3.2 Synchronous RAM
            1. 7.10.9.3.2.1 EMIF Synchronous Memory Timing Requirements
            2. 7.10.9.3.2.2 EMIF Synchronous Memory Switching Characteristics
            3. 7.10.9.3.2.3 EMIF Synchronous Memory Timing Diagrams
    11. 7.11 C28x Analog Peripherals
      1. 7.11.1 Analog Subsystem
      2. 7.11.2 Analog-to-Digital Converter (ADC)
        1. 7.11.2.1 Result Register Mapping
        2. 7.11.2.2 ADC Configurability
          1. 7.11.2.2.1 Signal Mode
        3. 7.11.2.3 ADC Electrical Data and Timing
          1. 7.11.2.3.1 ADC Operating Conditions (16-bit Differential)
            1. 7.11.2.3.1.1 ADC Operating Conditions (16-bit Differential) Notes
          2. 7.11.2.3.2 ADC Characteristics (16-bit Differential)
          3. 7.11.2.3.3 ADC Operating Conditions (16-bit Single-Ended)
            1. 7.11.2.3.3.1 ADC Operating Conditions (16-bit Single-Ended) Notes
          4. 7.11.2.3.4 ADC Characteristics (16-bit Single-Ended)
          5. 7.11.2.3.5 ADC Operating Conditions (12-bit Single-Ended)
            1. 7.11.2.3.5.1 ADC Operating Conditions (12-bit Single-Ended) Notes
          6. 7.11.2.3.6 ADC Characteristics (12-bit Single-Ended)
          7. 7.11.2.3.7 ADCEXTSOC Timing Requirements
          8. 7.11.2.3.8 ADC Input Models
            1. 7.11.2.3.8.1 Single-Ended Input Model Parameters (12-bit Resolution)
            2. 7.11.2.3.8.2 Single-Ended Input Model Parameters (16-bit Resolution)
            3. 7.11.2.3.8.3 Single-Ended Input Model
            4. 7.11.2.3.8.4 Differential Input Model Parameters (16-bit Resolution)
            5. 7.11.2.3.8.5 Differential Input Model
          9. 7.11.2.3.9 ADC Timing Diagrams
            1. 7.11.2.3.9.1 ADC Timings in 12-Bit Mode (SYSCLK Cycles)
            2. 7.11.2.3.9.2 ADC Timings in 16-Bit Mode
        4. 7.11.2.4 Temperature Sensor Electrical Data and Timing
          1. 7.11.2.4.1 Temperature Sensor Characteristics
      3. 7.11.3 Comparator Subsystem (CMPSS)
        1. 7.11.3.1 CMPSS Electrical Data and Timing
          1. 7.11.3.1.1 Comparator Electrical Characteristics
          2. 7.11.3.1.2 CMPSS Comparator Input Referred Offset and Hysteresis
          3. 7.11.3.1.3 CMPSS DAC Static Electrical Characteristics
          4. 7.11.3.1.4 CMPSS Illustrative Graphs
      4. 7.11.4 Buffered Digital-to-Analog Converter (DAC)
        1. 7.11.4.1 Buffered DAC Electrical Data and Timing
          1. 7.11.4.1.1 Buffered DAC Operating Conditions
          2. 7.11.4.1.2 Buffered DAC Electrical Characteristics
          3. 7.11.4.1.3 Buffered DAC Notes and Illustrative Graphs
    12. 7.12 C28x Control Peripherals
      1. 7.12.1 Enhanced Capture and High-Resolution Capture (eCAP, HRCAP)
        1. 7.12.1.1 eCAP Synchronization
        2. 7.12.1.2 eCAP Electrical Data and Timing
          1. 7.12.1.2.1 eCAP Timing Requirements
          2. 7.12.1.2.2 eCAP Switching Charcteristics
        3. 7.12.1.3 HRCAP Electrical Data and Timing
          1. 7.12.1.3.1 HRCAP Switching Characteristics
          2. 7.12.1.3.2 HRCAP Graphs
      2. 7.12.2 Enhanced Pulse Width Modulator (ePWM)
        1. 7.12.2.1 Control Peripherals Synchronization
        2. 7.12.2.2 ePWM Electrical Data and Timing
          1. 7.12.2.2.1 ePWM Timing Requirements
          2. 7.12.2.2.2 ePWM Switching Characteristics
          3. 7.12.2.2.3 Trip-Zone Input Timing
            1. 7.12.2.2.3.1 Trip-Zone Input Timing Requirements
        3. 7.12.2.3 External ADC Start-of-Conversion Electrical Data and Timing
          1. 7.12.2.3.1 External ADC Start-of-Conversion Switching Characteristics
      3. 7.12.3 High-Resolution Pulse Width Modulator (HRPWM)
        1. 7.12.3.1 HRPWM Electrical Data and Timing
          1. 7.12.3.1.1 High-Resolution PWM Characteristics
      4. 7.12.4 Enhanced Quadrature Encoder Pulse (eQEP)
        1. 7.12.4.1 eQEP Electrical Data and Timing
          1. 7.12.4.1.1 eQEP Timing Requirements
          2. 7.12.4.1.2 eQEP Switching Characteristics
      5. 7.12.5 Sigma-Delta Filter Module (SDFM)
        1. 7.12.5.1 SDFM Electrical Data and Timing (Using ASYNC)
          1. 7.12.5.1.1 SDFM Timing Requirements When Using Asynchronous GPIO (ASYNC) Option
          2. 7.12.5.1.2 SDFM Timing Diagram
    13. 7.13 C28x Communications Peripherals
      1. 7.13.1 Controller Area Network (CAN)
      2. 7.13.2 Fast Serial Interface (FSI)
        1. 7.13.2.1 FSI Transmitter
          1. 7.13.2.1.1 FSITX Electrical Data and Timing
            1. 7.13.2.1.1.1 FSITX Switching Characteristics
            2. 7.13.2.1.1.2 FSITX Timings
        2. 7.13.2.2 FSI Receiver
          1. 7.13.2.2.1 FSIRX Electrical Data and Timing
            1. 7.13.2.2.1.1 FSIRX Timing Requirements
            2. 7.13.2.2.1.2 FSIRX Switching Characteristics
            3. 7.13.2.2.1.3 FSIRX Timing Diagram
        3. 7.13.2.3 SPI Signaling Mode
          1. 7.13.2.3.1 FSITX SPI Signaling Mode Electrical Data and Timing
            1. 7.13.2.3.1.1 FSITX SPI Signaling Mode Switching Characteristics
            2. 7.13.2.3.1.2 FSITX SPI Signaling Mode Timings
      3. 7.13.3 Inter-Integrated Circuit (I2C)
        1. 7.13.3.1 I2C Electrical Data and Timing
          1. 7.13.3.1.1 I2C Timing Requirements
          2. 7.13.3.1.2 I2C Switching Characteristics
          3. 7.13.3.1.3 I2C Timing Diagram
      4. 7.13.4 Multichannel Buffered Serial Port (McBSP)
        1. 7.13.4.1 McBSP Electrical Data and Timing
          1. 7.13.4.1.1 McBSP Transmit and Receive Timing
            1. 7.13.4.1.1.1 McBSP Timing Requirements
            2. 7.13.4.1.1.2 McBSP Switching Characteristics
            3. 7.13.4.1.1.3 McBSP Receive and Transmit Timing Diagrams
          2. 7.13.4.1.2 McBSP as SPI Master or Slave Timing
            1. 7.13.4.1.2.1 McBSP as SPI Master Timing Requirements
            2. 7.13.4.1.2.2 McBSP as SPI Master Switching Characteristics
            3. 7.13.4.1.2.3 McBSP as SPI Slave Timing Requirements
            4. 7.13.4.1.2.4 McBSP as SPI Slave Switching Characteristics
            5. 7.13.4.1.2.5 McBSP as SPI Master or Slave Timing Diagrams
      5. 7.13.5 Power Management Bus (PMBus)
        1. 7.13.5.1 PMBus Electrical Data and Timing
          1. 7.13.5.1.1 PMBus Electrical Characteristics
          2. 7.13.5.1.2 PMBus Fast Mode Switching Characteristics
          3. 7.13.5.1.3 PMBus Standard Mode Switching Characteristics
      6. 7.13.6 Serial Communications Interface (SCI)
      7. 7.13.7 Serial Peripheral Interface (SPI)
        1. 7.13.7.1 SPI Electrical Data and Timing
          1. 7.13.7.1.1 SPI Master Mode Timings
            1. 7.13.7.1.1.1 SPI Master Mode Timing Requirements
            2. 7.13.7.1.1.2 SPI Master Mode Switching Characteristics (Clock Phase = 0)
            3. 7.13.7.1.1.3 SPI Master Mode Switching Characteristics (Clock Phase = 1)
            4. 7.13.7.1.1.4 SPI Master Mode External Timing
          2. 7.13.7.1.2 SPI Slave Mode Timings
            1. 7.13.7.1.2.1 SPI Slave Mode Timing Requirements
            2. 7.13.7.1.2.2 SPI Slave Mode Switching Characteristics
            3. 7.13.7.1.2.3 SPI Slave Mode External Timing
      8. 7.13.8 EtherCAT Slave Controller (ESC)
        1. 7.13.8.1 ESC Features
        2. 7.13.8.2 ESC Subsystem Integrated Features
        3. 7.13.8.3 EtherCAT IP Block Diagram
        4. 7.13.8.4 EtherCAT Electrical Data and Timing
          1. 7.13.8.4.1 EtherCAT Timing Requirements
          2. 7.13.8.4.2 EtherCAT Switching Characteristics
          3. 7.13.8.4.3 EtherCAT Timing Diagrams
      9. 7.13.9 Universal Serial Bus (USB) Controller
        1. 7.13.9.1 USB Electrical Data and Timing
          1. 7.13.9.1.1 USB Input Ports DP and DM Timing Requirements
          2. 7.13.9.1.2 USB Output Ports DP and DM Switching Characteristics
    14. 7.14 Connectivity Manager (CM) Peripherals
      1. 7.14.1 Modular Controller Area Network (MCAN) [CAN FD]
      2. 7.14.2 Ethernet Media Access Controller (EMAC)
        1. 7.14.2.1 MAC Features
          1. 7.14.2.1.1 MAC Tx and Rx Features
          2. 7.14.2.1.2 MAC Tx Features
          3. 7.14.2.1.3 MAC Rx Features
        2. 7.14.2.2 Ethernet Electrical Data and Timing
          1. 7.14.2.2.1 Ethernet Timing Requirements
          2. 7.14.2.2.2 Ethernet Switching Characteristics
          3. 7.14.2.2.3 Ethernet Timing Diagrams
        3. 7.14.2.3 Ethernet REVMII Electrical Data and Timing
          1. 7.14.2.3.1 Ethernet REVMII Timing Requirements
          2. 7.14.2.3.2 Ethernet REVMII Switching Characteristics
      3. 7.14.3 Inter-Integrated Circuit (CM-I2C)
        1. 7.14.3.1 CM-I2C Electrical Data and Timing
          1. 7.14.3.1.1 CM-I2C Timing Requirements
          2. 7.14.3.1.2 CM-I2C Switching Characteristics
          3. 7.14.3.1.3 CM-I2C Timing Diagram
      4. 7.14.4 Synchronous Serial Interface (SSI)
        1. 7.14.4.1 SSI Electrical Data and Timing
          1. 7.14.4.1.1 SSI Timing Requirements
          2. 7.14.4.1.2 SSI Characteristics
          3. 7.14.4.1.3 SSI Timing Diagrams
      5. 7.14.5 Universal Asynchronous Receiver/Transmitter (CM-UART)
      6. 7.14.6 Trace Port Interface Unit (TPIU)
        1. 7.14.6.1 TPIU Electrical Data and Timing
          1. 7.14.6.1.1 Trace Port Switching Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Memory
      1. 8.3.1 C28x Memory Map
      2. 8.3.2 C28x Flash Memory Map
      3. 8.3.3 EMIF Chip Select Memory Map
      4. 8.3.4 CM Memory Map
      5. 8.3.5 CM Flash Memory Map
      6. 8.3.6 Memory Types
        1. 8.3.6.1 Dedicated RAM (Mx and Dx RAM)
        2. 8.3.6.2 Local Shared RAM (LSx RAM)
        3. 8.3.6.3 Global Shared RAM (GSx RAM)
        4. 8.3.6.4 CPU Message RAM (CPU MSGRAM)
        5. 8.3.6.5 CLA Message RAM (CLA MSGRAM)
        6. 8.3.6.6 CLA - DMA Message RAM (CLA-DMA MSGRAM)
        7. 8.3.6.7 CPUx - CM Message RAM (CPUx-CM MSGRAM)
        8. 8.3.6.8 Dedicated RAM (C0/C1 RAM)
        9. 8.3.6.9 Shared RAM (E0 and Sx RAM)
    4. 8.4 Identification
    5. 8.5 Bus Architecture – Peripheral Connectivity
    6. 8.6 Boot ROM and Peripheral Booting
      1. 8.6.1 Device Boot
      2. 8.6.2 Device Boot Modes
      3. 8.6.3 Device Boot Configurations
      4. 8.6.4 GPIO Assignments for CPU1
    7. 8.7 Dual Code Security Module (DCSM)
    8. 8.8 C28x (CPU1/CPU2) Subsystem
      1. 8.8.1  C28x Processor
        1. 8.8.1.1 Floating-Point Unit
        2. 8.8.1.2 Trigonometric Math Unit
        3. 8.8.1.3 Fast Integer Division Unit
        4. 8.8.1.4 VCRC Unit
      2. 8.8.2  Embedded Real-Time Analysis and Diagnostic (ERAD)
      3. 8.8.3  Background CRC-32 (BGCRC)
      4. 8.8.4  Control Law Accelerator (CLA)
      5. 8.8.5  Direct Memory Access (DMA)
      6. 8.8.6  Interprocessor Communication (IPC) Module
      7. 8.8.7  C28x Timers
      8. 8.8.8  Dual-Clock Comparator (DCC)
        1. 8.8.8.1 Features
        2. 8.8.8.2 Mapping of DCCx (DCC0, DCC1, and DCC2) Clock Source Inputs
      9. 8.8.9  Nonmaskable Interrupt With Watchdog Timer (NMIWD)
      10. 8.8.10 Watchdog
      11. 8.8.11 Configurable Logic Block (CLB)
    9. 8.9 Connectivity Manager (CM) Subsystem
      1. 8.9.1  Arm Cortex-M4 Processor
      2. 8.9.2  Nested Vectored Interrupt Controller (NVIC)
      3. 8.9.3  Advance Encryption Standard (AES) Accelerator
      4. 8.9.4  Generic Cyclic Redundancy Check (GCRC) Module
      5. 8.9.5  CM Nonmaskable Interrupt (CMNMI) Module
      6. 8.9.6  Memory Protection Unit (MPU)
      7. 8.9.7  Micro Direct Memory Access (µDMA)
      8. 8.9.8  Watchdog
      9. 8.9.9  CM Clocking
        1. 8.9.9.1 CM Clock Sources
      10. 8.9.10 CM Timers
  9. Applications, Implementation, and Layout
    1. 9.1 TI Reference Design
  10. 10Device and Documentation Support
    1. 10.1 Device and Development Support Tool Nomenclature
    2. 10.2 Markings
    3. 10.3 Tools and Software
    4. 10.4 Documentation Support
    5. 10.5 Support Resources
    6. 10.6 Trademarks
    7. 10.7 Electrostatic Discharge Caution
    8. 10.8 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • ZWT|337
  • PTP|176
Thermal pad, mechanical data (Package|Pins)
Orderable Information

GPIO Muxed Pins Table

Table 6-7 GPIO Muxed Pins
0, 4, 8, 1212356791011131415ALT
GPIO0EPWM1AI2CA_SDACM-I2CA_SDAESC_GPI0FSITXA_D0
GPIO1EPWM1BMFSRBI2CA_SCLCM-I2CA_SCLESC_GPI1FSITXA_D1
GPIO2EPWM2AOUTPUTXBAR1I2CB_SDAESC_GPI2FSITXA_CLK
GPIO3EPWM2BOUTPUTXBAR2MCLKRBOUTPUTXBAR2I2CB_SCLESC_GPI3FSIRXA_D0
GPIO4EPWM3AOUTPUTXBAR3CANA_TXMCAN_TXESC_GPI4FSIRXA_D1
GPIO5EPWM3BMFSRAOUTPUTXBAR3CANA_RXMCAN_RXESC_GPI5FSIRXA_CLK
GPIO6EPWM4AOUTPUTXBAR4EXTSYNCOUTEQEP3_ACANB_TXESC_GPI6FSITXB_D0
GPIO7EPWM4BMCLKRAOUTPUTXBAR5EQEP3_BCANB_RXESC_GPI7FSITXB_D1
GPIO8EPWM5ACANB_TXADCSOCAOEQEP3_STROBESCIA_TXMCAN_TXESC_GPO0FSITXB_CLKFSITXA_D1FSIRXA_D0
GPIO9EPWM5BSCIB_TXOUTPUTXBAR6EQEP3_INDEXSCIA_RXESC_GPO1FSIRXB_D0FSITXA_D0FSIRXA_CLK
GPIO10EPWM6ACANB_RXADCSOCBOEQEP1_ASCIB_TXMCAN_RXESC_GPO2FSIRXB_D1FSITXA_CLKFSIRXA_D1
GPIO11EPWM6BSCIB_RXOUTPUTXBAR7EQEP1_BSCIB_RXESC_GPO3FSIRXB_CLKFSIRXA_D1
GPIO12EPWM7ACANB_TXMDXBEQEP1_STROBESCIC_TXESC_GPO4FSIRXC_D0FSIRXA_D0
GPIO13EPWM7BCANB_RXMDRBEQEP1_INDEXSCIC_RXESC_GPO5FSIRXC_D1FSIRXA_CLK
GPIO14EPWM8ASCIB_TXMCLKXBOUTPUTXBAR3ESC_GPO6FSIRXC_CLK
GPIO15EPWM8BSCIB_RXMFSXBOUTPUTXBAR4ESC_GPO7FSIRXD_D0
GPIO16SPIA_SIMOCANB_TXOUTPUTXBAR7EPWM9ASD1_D1SSIA_TXFSIRXD_D1
GPIO17SPIA_SOMICANB_RXOUTPUTXBAR8EPWM9BSD1_C1SSIA_RXFSIRXD_CLK
GPIO18SPIA_CLKSCIB_TXCANA_RXEPWM10ASD1_D2MCAN_RXEMIF1_CS2nSSIA_CLKFSIRXE_D0
GPIO19SPIA_STEnSCIB_RXCANA_TXEPWM10BSD1_C2MCAN_TXEMIF1_CS3nSSIA_FSSFSIRXE_D1
GPIO20EQEP1_AMDXACANB_TXEPWM11ASD1_D3EMIF1_BA0TRACE_DATA0FSIRXE_CLKSPIC_SIMO
GPIO21EQEP1_BMDRACANB_RXEPWM11BSD1_C3EMIF1_BA1TRACE_DATA1FSIRXF_D0SPIC_SOMI
GPIO22EQEP1_STROBEMCLKXASCIB_TXEPWM12ASPIB_CLKSD1_D4MCAN_TXEMIF1_RASTRACE_DATA2FSIRXF_D1SPIC_CLK
GPIO23EQEP1_INDEXMFSXASCIB_RXEPWM12BSPIB_STEnSD1_C4MCAN_RXEMIF1_CASTRACE_DATA3FSIRXF_CLKSPIC_STEn
GPIO24OUTPUTXBAR1EQEP2_AMDXBSPIB_SIMOSD2_D1PMBUSA_SCLEMIF1_DQM0TRACE_CLKEPWM13AFSIRXG_D0
GPIO25OUTPUTXBAR2EQEP2_BMDRBSPIB_SOMISD2_C1PMBUSA_SDAEMIF1_DQM1TRACE_SWOEPWM13BFSITXA_D1FSIRXG_D1
GPIO26OUTPUTXBAR3EQEP2_INDEXMCLKXBOUTPUTXBAR3SPIB_CLKSD2_D2PMBUSA_ALERTEMIF1_DQM2ESC_MDIO_CLKEPWM14AFSITXA_D0FSIRXG_CLK
GPIO27OUTPUTXBAR4EQEP2_STROBEMFSXBOUTPUTXBAR4SPIB_STEnSD2_C2PMBUSA_CTLEMIF1_DQM3ESC_MDIO_DATAEPWM14BFSITXA_CLKFSIRXH_D0
GPIO28SCIA_RXEMIF1_CS4nOUTPUTXBAR5EQEP3_ASD2_D3EMIF1_CS2nEPWM15AFSIRXH_D1
GPIO29SCIA_TXEMIF1_SDCKEOUTPUTXBAR6EQEP3_BSD2_C3EMIF1_CS3nESC_LATCH0ESC_I2C_SDAEPWM15BESC_SYNC0FSIRXH_CLK
GPIO30CANA_RXEMIF1_CLKMCAN_RXOUTPUTXBAR7EQEP3_STROBESD2_D4EMIF1_CS4nESC_LATCH1ESC_I2C_SCLEPWM16AESC_SYNC1SPID_SIMO
GPIO31CANA_TXEMIF1_WEnMCAN_TXOUTPUTXBAR8EQEP3_INDEXSD2_C4EMIF1_RNWI2CA_SDACM-I2CA_SDAEPWM16BSPID_SOMI
GPIO32I2CA_SDAEMIF1_CS0nSPIA_SIMOCLB_OUTPUTXBAR1EMIF1_OEnI2CA_SCLCM-I2CA_SCLSPID_CLK
GPIO33I2CA_SCLEMIF1_RNWSPIA_SOMICLB_OUTPUTXBAR2EMIF1_BA0SPID_STEn
GPIO34OUTPUTXBAR1EMIF1_CS2nSPIA_CLKI2CB_SDACLB_OUTPUTXBAR3EMIF1_BA1ESC_LATCH0ENET_MII_CRSSCIA_TXESC_SYNC0
GPIO35SCIA_RXEMIF1_CS3nSPIA_STEnI2CB_SCLCLB_OUTPUTXBAR4EMIF1_A0ESC_LATCH1ENET_MII_COLESC_SYNC1
GPIO36SCIA_TXEMIF1_WAITCANA_RXCLB_OUTPUTXBAR5EMIF1_A1MCAN_RXSD1_D1
GPIO37OUTPUTXBAR2EMIF1_OEnCANA_TXCLB_OUTPUTXBAR6EMIF1_A2MCAN_TXSD1_D2
GPIO38EMIF1_A0SCIC_TXCANB_TXCLB_OUTPUTXBAR7EMIF1_A3ENET_MII_RX_DVENET_MII_CRSSD1_D3
GPIO39EMIF1_A1SCIC_RXCANB_RXCLB_OUTPUTXBAR8EMIF1_A4ENET_MII_RX_ERRENET_MII_COLSD1_D4
GPIO40EMIF1_A2I2CB_SDAENET_MII_CRSESC_I2C_SDA
GPIO41EMIF1_A3I2CB_SCLENET_REVMII_MDIO_RSTENET_MII_COLESC_I2C_SCL
GPIO42I2CA_SDAENET_MDIO_CLKUARTA_TXSCIA_TXUSB0DM
GPIO43I2CA_SCLENET_MDIO_DATAUARTA_RXSCIA_RXUSB0DP
GPIO44EMIF1_A4ENET_MII_TX_CLKESC_TX1_CLK
GPIO45EMIF1_A5ENET_MII_TX_ENESC_TX1_ENA
GPIO46EMIF1_A6SCID_RXENET_MII_TX_ERRESC_MDIO_CLK
GPIO47EMIF1_A7SCID_TXENET_PPS0ESC_MDIO_DATA
GPIO48OUTPUTXBAR3EMIF1_A8SCIA_TXSD1_D1ENET_PPS1ESC_PHY_CLK
GPIO49OUTPUTXBAR4EMIF1_A9SCIA_RXSD1_C1EMIF1_A5ENET_MII_RX_CLKSD2_D1FSITXA_D0
GPIO50EQEP1_AEMIF1_A10SPIC_SIMOSD1_D2EMIF1_A6ENET_MII_RX_DVSD2_D2FSITXA_D1
GPIO51EQEP1_BEMIF1_A11SPIC_SOMISD1_C2EMIF1_A7ENET_MII_RX_ERRSD2_D3FSITXA_CLK
GPIO52EQEP1_STROBEEMIF1_A12SPIC_CLKSD1_D3EMIF1_A8ENET_MII_RX_DATA0SD2_D4FSIRXA_D0
GPIO53EQEP1_INDEXEMIF1_D31EMIF2_D15SPIC_STEnSD1_C3EMIF1_A9ENET_MII_RX_DATA1SD1_C1FSIRXA_D1
GPIO54SPIA_SIMOEMIF1_D30EMIF2_D14EQEP2_ASCIB_TXSD1_D4EMIF1_A10ENET_MII_RX_DATA2SD1_C2FSIRXA_CLKSSIA_TX
GPIO55SPIA_SOMIEMIF1_D29EMIF2_D13EQEP2_BSCIB_RXSD1_C4EMIF1_D0ENET_MII_RX_DATA3SD1_C3FSITXB_D0SSIA_RX
GPIO56SPIA_CLKEMIF1_D28EMIF2_D12EQEP2_STROBESCIC_TXSD2_D1EMIF1_D1I2CA_SDAENET_MII_TX_ENSD1_C4FSITXB_CLKSSIA_CLK
GPIO57SPIA_STEnEMIF1_D27EMIF2_D11EQEP2_INDEXSCIC_RXSD2_C1EMIF1_D2I2CA_SCLENET_MII_TX_ERRFSITXB_D1SSIA_FSS
GPIO58MCLKRAEMIF1_D26EMIF2_D10OUTPUTXBAR1SPIB_CLKSD2_D2EMIF1_D3ESC_LED_LINK0_ACTIVEENET_MII_TX_CLKSD2_C2FSIRXB_D0SPIA_SIMO
GPIO59MFSRAEMIF1_D25EMIF2_D9OUTPUTXBAR2SPIB_STEnSD2_C2EMIF1_D4ESC_LED_LINK1_ACTIVEENET_MII_TX_DATA0SD2_C3FSIRXB_D1SPIA_SOMI
GPIO60MCLKRBEMIF1_D24EMIF2_D8OUTPUTXBAR3SPIB_SIMOSD2_D3EMIF1_D5ESC_LED_ERRENET_MII_TX_DATA1SD2_C4FSIRXB_CLKSPIA_CLK
GPIO61MFSRBEMIF1_D23EMIF2_D7OUTPUTXBAR4SPIB_SOMISD2_C3EMIF1_D6ESC_LED_RUNENET_MII_TX_DATA2CANA_RXSPIA_STEn
GPIO62SCIC_RXEMIF1_D22EMIF2_D6EQEP3_ACANA_RXSD2_D4EMIF1_D7ESC_LED_STATE_RUNENET_MII_TX_DATA3CANA_TX
GPIO63SCIC_TXEMIF1_D21EMIF2_D5EQEP3_BCANA_TXSD2_C4SSIA_TXENET_MII_RX_DATA0SD1_D1ESC_RX1_DATA0SPIB_SIMO
GPIO64EMIF1_D20EMIF2_D4EQEP3_STROBESCIA_RXSSIA_RXENET_MII_RX_DVENET_MII_RX_DATA1SD1_C1ESC_RX1_DATA1SPIB_SOMI
GPIO65EMIF1_D19EMIF2_D3EQEP3_INDEXSCIA_TXSSIA_CLKENET_MII_RX_ERRENET_MII_RX_DATA2SD1_D2ESC_RX1_DATA2SPIB_CLK
GPIO66EMIF1_D18EMIF2_D2I2CB_SDASSIA_FSSENET_MII_RX_DATA0ENET_MII_RX_DATA3SD1_C2ESC_RX1_DATA3SPIB_STEn
GPIO67EMIF1_D17EMIF2_D1ENET_MII_RX_CLKENET_REVMII_MDIO_RSTSD1_D3
GPIO68EMIF1_D16EMIF2_D0ENET_MII_INTRSD1_C3ESC_PHY1_LINKSTATUS
GPIO69EMIF1_D15I2CB_SCLENET_MII_TX_ENENET_MII_RX_CLKSD1_D4ESC_RX1_CLKSPIC_SIMO
GPIO70EMIF1_D14CANA_RXSCIB_TXMCAN_RXENET_MII_RX_DVSD1_C4ESC_RX1_DVSPIC_SOMI
GPIO71EMIF1_D13CANA_TXSCIB_RXMCAN_TXENET_MII_RX_DATA0ENET_MII_RX_ERRESC_RX1_ERRSPIC_CLK
GPIO72EMIF1_D12CANB_TXSCIC_TXENET_MII_RX_DATA1ENET_MII_TX_DATA3ESC_TX1_DATA3SPIC_STEn
GPIO73EMIF1_D11XCLKOUTCANB_RXSCIC_RXENET_RMII_CLKENET_MII_TX_DATA2SD2_D2ESC_TX1_DATA2
GPIO74EMIF1_D10MCAN_TXENET_MII_TX_DATA1SD2_C2ESC_TX1_DATA1
GPIO75EMIF1_D9MCAN_RXENET_MII_TX_DATA0SD2_D3ESC_TX1_DATA0
GPIO76EMIF1_D8SCID_TXENET_MII_RX_ERRSD2_C3ESC_PHY_RESETn
GPIO77EMIF1_D7SCID_RXSD2_D4ESC_RX0_CLK
GPIO78EMIF1_D6EQEP2_ASD2_C4ESC_RX0_DV
GPIO79EMIF1_D5EQEP2_BSD2_D1ESC_RX0_ERR
GPIO80EMIF1_D4EQEP2_STROBESD2_C1ESC_RX0_DATA0
GPIO81EMIF1_D3EQEP2_INDEXESC_RX0_DATA1
GPIO82EMIF1_D2ESC_RX0_DATA2
GPIO83EMIF1_D1ESC_RX0_DATA3
GPIO84SCIA_TXMDXBUARTA_TXESC_TX0_ENAMDXA
GPIO85EMIF1_D0SCIA_RXMDRBUARTA_RXESC_TX0_CLKMDRA
GPIO86EMIF1_A13EMIF1_CASSCIB_TXMCLKXBESC_PHY0_LINKSTATUSMCLKXA
GPIO87EMIF1_A14EMIF1_RASSCIB_RXMFSXBEMIF1_DQM3ESC_TX0_DATA0MFSXA
GPIO88EMIF1_A15EMIF1_DQM0EMIF1_DQM1ESC_TX0_DATA1
GPIO89EMIF1_A16EMIF1_DQM1SCIC_TXEMIF1_CASESC_TX0_DATA2
GPIO90EMIF1_A17EMIF1_DQM2SCIC_RXEMIF1_RASESC_TX0_DATA3
GPIO91EMIF1_A18EMIF1_DQM3I2CA_SDAEMIF1_DQM2PMBUSA_SCLSSIA_TXFSIRXF_D0CLB_OUTPUTXBAR1SPID_SIMO
GPIO92EMIF1_A19EMIF1_BA1I2CA_SCLEMIF1_DQM0PMBUSA_SDASSIA_RXFSIRXF_D1CLB_OUTPUTXBAR2SPID_SOMI
GPIO93EMIF1_BA0SCID_TXPMBUSA_ALERTSSIA_CLKFSIRXF_CLKCLB_OUTPUTXBAR3SPID_CLK
GPIO94SCID_RXEMIF1_BA1PMBUSA_CTLSSIA_FSSFSIRXG_D0CLB_OUTPUTXBAR4SPID_STEn
GPIO95EMIF2_A12FSIRXG_D1CLB_OUTPUTXBAR5
GPIO96EMIF2_DQM1EQEP1_AFSIRXG_CLKCLB_OUTPUTXBAR6
GPIO97EMIF2_DQM0EQEP1_BFSIRXH_D0CLB_OUTPUTXBAR7
GPIO98EMIF2_A0EQEP1_STROBEFSIRXH_D1CLB_OUTPUTXBAR8
GPIO99EMIF2_A1EQEP1_INDEXFSIRXH_CLK
GPIO100EMIF2_A2EQEP2_ASPIC_SIMOESC_GPI0FSITXA_D0
GPIO101EMIF2_A3EQEP2_BSPIC_SOMIESC_GPI1FSITXA_D1
GPIO102EMIF2_A4EQEP2_STROBESPIC_CLKESC_GPI2FSITXA_CLK
GPIO103EMIF2_A5EQEP2_INDEXSPIC_STEnESC_GPI3FSIRXA_D0
GPIO104I2CA_SDAEMIF2_A6EQEP3_ASCID_TXESC_GPI4CM-I2CA_SDAFSIRXA_D1
GPIO105I2CA_SCLEMIF2_A7EQEP3_BSCID_RXESC_GPI5CM-I2CA_SCLFSIRXA_CLKENET_MDIO_CLK
GPIO106EMIF2_A8EQEP3_STROBESCIC_TXESC_GPI6FSITXB_D0ENET_MDIO_DATA
GPIO107EMIF2_A9EQEP3_INDEXSCIC_RXESC_GPI7FSITXB_D1ENET_REVMII_MDIO_RST
GPIO108EMIF2_A10ESC_GPI8FSITXB_CLKENET_MII_INTR
GPIO109EMIF2_A11ESC_GPI9ENET_MII_CRS
GPIO110EMIF2_WAITESC_GPI10FSIRXB_D0ENET_MII_COL
GPIO111EMIF2_BA0ESC_GPI11FSIRXB_D1ENET_MII_RX_CLK
GPIO112EMIF2_BA1ESC_GPI12FSIRXB_CLKENET_MII_RX_DV
GPIO113EMIF2_CASESC_GPI13ENET_MII_RX_ERR
GPIO114EMIF2_RASESC_GPI14ENET_MII_RX_DATA0
GPIO115EMIF2_CS0nOUTPUTXBAR5ESC_GPI15FSIRXC_D0ENET_MII_RX_DATA1
GPIO116EMIF2_CS2nOUTPUTXBAR6ESC_GPI16FSIRXC_D1ENET_MII_RX_DATA2
GPIO117EMIF2_SDCKEESC_GPI17FSIRXC_CLKENET_MII_RX_DATA3
GPIO118EMIF2_CLKESC_GPI18FSIRXD_D0ENET_MII_TX_EN
GPIO119EMIF2_RNWESC_GPI19FSIRXD_D1ENET_MII_TX_ERR
GPIO120EMIF2_WEnESC_GPI20FSIRXD_CLKENET_MII_TX_CLK
GPIO121EMIF2_OEnESC_GPI21FSIRXE_D0ENET_MII_TX_DATA0
GPIO122EMIF2_D15SPIC_SIMOSD1_D1ESC_GPI22ENET_MII_TX_DATA1
GPIO123EMIF2_D14SPIC_SOMISD1_C1ESC_GPI23ENET_MII_TX_DATA2
GPIO124EMIF2_D13SPIC_CLKSD1_D2ESC_GPI24ENET_MII_TX_DATA3
GPIO125EMIF2_D12SPIC_STEnSD1_C2ESC_GPI25FSIRXE_D1ESC_LATCH0
GPIO126EMIF2_D11SD1_D3ESC_GPI26FSIRXE_CLKESC_LATCH1
GPIO127EMIF2_D10SD1_C3ESC_GPI27ESC_SYNC0
GPIO128EMIF2_D9SD1_D4ESC_GPI28ESC_SYNC1
GPIO129EMIF2_D8SD1_C4ESC_GPI29ESC_TX1_ENA
GPIO130EMIF2_D7SD2_D1ESC_GPI30ESC_TX1_CLK
GPIO131EMIF2_D6SD2_C1ESC_GPI31ESC_TX1_DATA0
GPIO132EMIF2_D5SD2_D2ESC_GPO0ESC_TX1_DATA1
GPIO133SD2_C2AUXCLKIN
GPIO134EMIF2_D4SD2_D3ESC_GPO1ESC_TX1_DATA2
GPIO135EMIF2_D3SCIA_TXSD2_C3ESC_GPO2ESC_TX1_DATA3
GPIO136EMIF2_D2SCIA_RXSD2_D4ESC_GPO3ESC_RX1_DV
GPIO137EPWM13AEMIF2_D1SCIB_TXSD2_C4ESC_GPO4ESC_RX1_CLK
GPIO138EPWM13BEMIF2_D0SCIB_RXESC_GPO5ESC_RX1_ERR
GPIO139EPWM14ASCIC_RXESC_GPO6ESC_RX1_DATA0
GPIO140EPWM14BSCIC_TXESC_GPO7ESC_RX1_DATA1
GPIO141EPWM15ASCID_RXESC_GPO8ESC_RX1_DATA2
GPIO142EPWM15BSCID_TXESC_GPO9ESC_RX1_DATA3
GPIO143EPWM16AESC_GPO10ESC_LED_LINK0_ACTIVE
GPIO144EPWM16BESC_GPO11ESC_LED_LINK1_ACTIVE
GPIO145EPWM1AESC_GPO12ESC_LED_ERR
GPIO146EPWM1BESC_GPO13ESC_LED_RUN
GPIO147EPWM2AESC_GPO14ESC_LED_STATE_RUN
GPIO148EPWM2BESC_GPO15ESC_PHY0_LINKSTATUS
GPIO149EPWM3AESC_GPO16ESC_PHY1_LINKSTATUS
GPIO150EPWM3BESC_GPO17ESC_I2C_SDA
GPIO151EPWM4AESC_GPO18ESC_I2C_SCL
GPIO152EPWM4BESC_GPO19ESC_MDIO_CLK
GPIO153EPWM5AESC_GPO20ESC_MDIO_DATA
GPIO154EPWM5BESC_GPO21ESC_PHY_CLK
GPIO155EPWM6AESC_GPO22ESC_PHY_RESETn
GPIO156EPWM6BESC_GPO23ESC_TX0_ENA
GPIO157EPWM7AESC_GPO24ESC_TX0_CLK
GPIO158EPWM7BESC_GPO25ESC_TX0_DATA0
GPIO159EPWM8AESC_GPO26ESC_TX0_DATA1
GPIO160EPWM8BESC_GPO27ESC_TX0_DATA2
GPIO161EPWM9AESC_GPO28ESC_TX0_DATA3
GPIO162EPWM9BESC_GPO29ESC_RX0_DV
GPIO163EPWM10AESC_GPO30ESC_RX0_CLK
GPIO164EPWM10BESC_GPO31ESC_RX0_ERR
GPIO165EPWM11AMDXAESC_RX0_DATA0
GPIO166EPWM11BMDRAESC_RX0_DATA1
GPIO167EPWM12AMCLKXAESC_RX0_DATA2
GPIO168EPWM12BMFSXAESC_RX0_DATA3