SLVSF07 July 2021 TPS7H5001-SP
During steady state operation, the input voltage of the TPS7H5001-SP must be between 4 V and 14 V. A minimum bypass capacitance of at least 0.1 µF is needed between VIN and AVSS. The input bypass capacitors should be placed as close to the controller as possible.
The voltage applied at VIN serves as the input for the internal regulator that generates the VLDO voltage (5 V). At input voltages less than 5 V, the VLDO voltage will follow the voltage at VIN. Recommended capacitance for VLDO is 1 µF. The EN and/or DCL pin can be tied to VLDO, but otherwise it is recommended to not externally load this pin due to limited output current capability.
A voltage divider connected between VIN and the EN pin can adjust the input voltage UVLO appropriately.