SLVSF07 July   2021 TPS7H5001-SP

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and VLDO
      2. 7.3.2  Startup
      3. 7.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Output Voltage Programming
      7. 7.3.7  Soft-Start (SS)
      8. 7.3.8  Switching Frequency and External Synchronization
        1. 7.3.8.1 Internal Oscillator Mode
        2. 7.3.8.2 External Synchronization Mode
        3. 7.3.8.3 Primary-Secondary Mode
      9. 7.3.9  Primary Switching Outputs (OUTA and OUTB)
      10. 7.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 7.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Duty Cycle Programmability
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Hiccup Mode Operation (HICC)
      16. 7.3.16 External Fault Protection (FAULT)
      17. 7.3.17 Slope Compensation (RSC)
      18. 7.3.18 Frequency Compensation
      19. 7.3.19 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistors
        3. 8.2.2.3  Dead Time
        4. 8.2.2.4  Leading Edge Blank Time
        5. 8.2.2.5  Soft-Start Capacitor
        6. 8.2.2.6  Transformer
        7. 8.2.2.7  Main Switching FETs
        8. 8.2.2.8  Synchronous Rectificier FETs
        9. 8.2.2.9  RCD Clamp
        10. 8.2.2.10 Output Inductor
        11. 8.2.2.11 Output Capacitance and Filter
        12. 8.2.2.12 Sense Resistor
        13. 8.2.2.13 Hiccup Capacitor
        14. 8.2.2.14 Frequency Compensation Components
        15. 8.2.2.15 Slope Compensation Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Transformer

The turns ratio and primary inductance of the transformer will be determined based on the target specifications of the converter. In order to calculate the maximum allowable turns ratio, a duty cycle limit must be selected for the design. Even though DCL will be connected to AVSS to impose a 50% duty cycle limit from the controller to ensure there is no overlap of the primary switching outputs, a maximum duty cycle of approximately 35% is targeted for the design in order to provide sufficient margin to the controller limit. This is due to the fact that the actual duty cycle is greater than calculated duty cycle when accounting for the converter efficiency, and to allow for duty cycle increases during load transient events. Equation 31 provides the formulate needed to calculate the maximum turns ratio for this design.

Equation 31.

VSR is estimated to be 0.5 V for the application and DLIM is 35% duty cycle limit that was selected. NPS_MAX is calculated using the values in Equation 32.

Equation 32.

A value of 2.5 is selected for the turns ratio for the design.

In order to design for the primary inductance of the transformer, the magnetizing current must be selected. The value of the magnetizing current is a trade-off between transformer size and efficiency, with larger magnetizing current leading to a smaller size due to lower required inductance, but also leading to lower efficiency. A magnetizing current equal to 6% of the output current was initially targeted for this design. With this value, the primary inductance can be calculated using Equation 36. The minimum duty cycle expected is needed for this calculation can be determined using Equation 34, where the estimated efficiency η for the converter used in the calculation is 85%.

Equation 33.
Equation 34.
Equation 35.
Equation 36.

Though the calculated value of LP is 33 μH, it may often be challenging to find the exact primary inductance value needed for the transformer design. As such, an inductance of 40 μH was used in the actual design.

The following equations detail the how to calculate transformer primary and secondary currents that are critical for proper design of the transformer. These equations are useful for defining the physical structure of the transformer. Note that these are ideal equations, and the final design should be optimized depending on the application.

Equation 37.
Equation 38.
Equation 39. GUID-20210617-CA0I-CBH1-6RLJ-LRGMKNFSVQC7-low.png
Equation 40. GUID-20210617-CA0I-Z8BF-BN5V-CMKSNQTTSQZR-low.png
Equation 41. GUID-20210617-CA0I-JJZW-7D2K-N9KNQV5K8FPL-low.png
Equation 42. GUID-20210617-CA0I-F22G-SVG8-HL4QGZ6XZ2FC-low.png
Equation 43. GUID-20210617-CA0I-TTZK-LTGM-G6VJLV79QNJT-low.png
Equation 44. GUID-20210617-CA0I-7SZS-JR59-KBFBPFCRMMPM-low.png
Equation 45. GUID-20210617-CA0I-KK2M-DSKT-NTBQBPFJ7C7G-low.png
Equation 46. GUID-20210617-CA0I-D6MH-FVJZ-7S16PD7JGXWB-low.png
Equation 47. GUID-20210617-CA0I-VR2G-CNZT-QDWBWMMVT9PK-low.png
Equation 48. GUID-20210617-CA0I-X6CN-HPBS-9RLFKRWPT1MK-low.png
Equation 49. GUID-20210620-CA0I-DF3H-HXCJ-B0KTKSPCH04R-low.png
Equation 50. GUID-20210620-CA0I-0SRQ-DVJP-V4WT3H2H4NM3-low.png
Equation 51.
Equation 52.
Equation 53. GUID-20210617-CA0I-8TSL-7RR3-R6KF5SZFCPHV-low.png
Equation 54. GUID-20210621-CA0I-SGFB-ZJLC-ZZNZDSCJRLMX-low.png