SLVSF07 July   2021 TPS7H5001-SP

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and VLDO
      2. 7.3.2  Startup
      3. 7.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Output Voltage Programming
      7. 7.3.7  Soft-Start (SS)
      8. 7.3.8  Switching Frequency and External Synchronization
        1. 7.3.8.1 Internal Oscillator Mode
        2. 7.3.8.2 External Synchronization Mode
        3. 7.3.8.3 Primary-Secondary Mode
      9. 7.3.9  Primary Switching Outputs (OUTA and OUTB)
      10. 7.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 7.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Duty Cycle Programmability
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Hiccup Mode Operation (HICC)
      16. 7.3.16 External Fault Protection (FAULT)
      17. 7.3.17 Slope Compensation (RSC)
      18. 7.3.18 Frequency Compensation
      19. 7.3.19 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Switching Frequency
        2. 8.2.2.2  Output Voltage Programming Resistors
        3. 8.2.2.3  Dead Time
        4. 8.2.2.4  Leading Edge Blank Time
        5. 8.2.2.5  Soft-Start Capacitor
        6. 8.2.2.6  Transformer
        7. 8.2.2.7  Main Switching FETs
        8. 8.2.2.8  Synchronous Rectificier FETs
        9. 8.2.2.9  RCD Clamp
        10. 8.2.2.10 Output Inductor
        11. 8.2.2.11 Output Capacitance and Filter
        12. 8.2.2.12 Sense Resistor
        13. 8.2.2.13 Hiccup Capacitor
        14. 8.2.2.14 Frequency Compensation Components
        15. 8.2.2.15 Slope Compensation Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Configuration and Functions

GUID-20210118-CA0I-NZSF-CB8T-F831W0K6XM3T-low.png Figure 5-1 HFT Package
22-Pin CFP With Thermal Pad
Top View
Table 5-1 Pin Functions
PIN I/O DESCRIPTION
NAME NO.
RT 1 I/O In internal oscillation mode, the RT pin must be populated with a resistor to AVSS. When the RT pin is floating, a 200-kHz to 4-MHz external clock is required at the SYNC pin. The frequency of the external clock must be twice the desired switching frequency.
PS 2 I/O Primary off to synchronous rectifier on dead-time set. Programmable through an external resistor to AVSS.
SP 3 I/O Synchronous rectifier off to primary on dead-time set. Programmable through an external resistor to AVSS.
LEB 4 I/O Leading edge blank time set. Programmable through an external resistor to AVSS.
HICC 5 I/O Cycle-by-cycle current limit time delay and hiccup time setting. Delay time and hiccup time determined by capacitor from HICC to AVSS. Connecting this pin to AVSS disables hiccup mode.
SYNC 6 I/O When the RT pin is floating, SYNC is configured as an input for a 200-kHz to 4-MHz external clock. In this case, the external clock input gets inverted and the system clock will run at half the frequency of the external clock input. When the RT pin is populated with a resistor to AVSS, SYNC outputs a 200-kHz to 4-MHz clock signal in phase with the switching frequency of the device.
DCL 7 I/O Duty cycle limit configurability. This pin can be connected to AVSS, left floating, or VLDO to set the maximum duty cycle to 50%, 75%, and 100% respectively.
EN 8 I Connecting the EN pin to the VLDO pin or external source greater than 0.6 V enables the device. In addition, input undervoltage lockout (UVLO) can be adjusted with two resistors.
VIN 9 I Input supply to the device. Input voltage range is from 4 V to 14 V.
OUTA 10 O Primary switching output A.
OUTB 11 O Primary switching output B. Active only when DCL = AVSS.
SRB 12 O Synchronous rectifier output B. Active only when DCL = AVSS.
SRA 13 O Synchronous rectifier output A.
AVSS 14 Ground of the device. The thermal pad, lid, and seal ring of the device are connected to ground.
VLDO 15 O Output of internal regulator. Requires at least 1-μF external capacitor to AVSS.
CS_ILIM 16 I/O Current sense for PWM control and cycle-by-cycle overcurrent protection. An input voltage over 1.05 V on CS_ILIM will trigger an overcurrent in the PWM controller.
FAULT 17 I Fault protection pin. When the rising threshold of the FAULT pin is exceeded, the outputs will stop switching. After the external voltage drops below the falling threshold, the device will restart after a set delay. Connect this pin to AVSS to disable FAULT.
REFCAP 18 O 1.2-V internal reference. Requires a 470-nF external capacitor to AVSS.
RSC 19 I/O A resistor from RSC to AVSS sets the desired slope compensation.
SS 20 I/O Soft start. An external capacitor connected to this pin sets the internal voltage reference rise time. The voltage on this pin overrides the internal reference. It can be used for tracking and sequencing.
VSENSE 21 I Inverting input of the error amplifier.
COMP 22 I/O Error amplifier output. Connect frequency compensation to this pin.