SLVSF07 July   2021 TPS7H5001-SP


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  VIN and VLDO
      2. 7.3.2  Startup
      3. 7.3.3  Enable and Undervoltage Lockout (UVLO)
      4. 7.3.4  Voltage Reference
      5. 7.3.5  Error Amplifier
      6. 7.3.6  Output Voltage Programming
      7. 7.3.7  Soft-Start (SS)
      8. 7.3.8  Switching Frequency and External Synchronization
        1. Internal Oscillator Mode
        2. External Synchronization Mode
        3. Primary-Secondary Mode
      9. 7.3.9  Primary Switching Outputs (OUTA and OUTB)
      10. 7.3.10 Synchronous Rectifier Outputs (SRA and SRB)
      11. 7.3.11 Dead Time and Leading Edge Blank Time Programmability (PS, SP, and LEB)
      12. 7.3.12 Pulse Skipping
      13. 7.3.13 Duty Cycle Programmability
      14. 7.3.14 Current Sense and PWM Generation (CS_ILIM)
      15. 7.3.15 Hiccup Mode Operation (HICC)
      16. 7.3.16 External Fault Protection (FAULT)
      17. 7.3.17 Slope Compensation (RSC)
      18. 7.3.18 Frequency Compensation
      19. 7.3.19 Thermal Shutdown
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1.  Switching Frequency
        2.  Output Voltage Programming Resistors
        3.  Dead Time
        4.  Leading Edge Blank Time
        5.  Soft-Start Capacitor
        6.  Transformer
        7.  Main Switching FETs
        8.  Synchronous Rectificier FETs
        9.  RCD Clamp
        10. Output Inductor
        11. Output Capacitance and Filter
        12. Sense Resistor
        13. Hiccup Capacitor
        14. Frequency Compensation Components
        15. Slope Compensation Resistor
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • HFT|22
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Output Capacitance and Filter

Generally, there are two different calculations that can be used to determine the output capacitance required for the converter. The first calculates the amount of capacitance required to meet the maximum allowable voltage deviation at the output in response to a worst-case load transient as shown in Equation 62. The second, shown in Equation 64, determines the amount of output capacitance that is needed to meet the output voltage ripple requirements of the design. Once the two different calculations are performed, the maximum of these should be chosen as the output capacitance for the design. The calculations are shown for target voltage ripple of 2% of the output voltage and maximum allowable voltage deviation of 2.5% of the output voltage.

Equation 62.
Equation 63.
Equation 64.
Equation 65.

Based on the calculations, at least 1.3 mF of output capacitance is required. When selecting capacitors, consider any derating of capacitance that is needed to account for aging, temperature, and DC bias.

For space-grade converter designs, there is another consideration when selecting the output capacitance. This is the impact of radiation induced single event transients (SETs). Single energetic particle strikes can lead to momentary variation in the PWM variation of the controller, which in turn can lead to output voltage transients in the converter. Thus, even though the value above provides a minimum value to account for voltage ripple and/or load transients, additional capacitance is likely needed to for adequate SET mitigation. For the design example, approximately 2.3 mF of total output capacitance was used.

An additional output filter can be used to further reduce the noise of the output stage if deemed necessary. This output filter consists of an additional inductor and a small amount of ceramic capacitance. This ceramic capacitance is placed immediately downstream of the main output inductor that was determined in Section The filter inductance is then located between the added ceramic capacitance and the bulk output capacitance that was determined to be required for the design. This approach can drastically reduce the output voltage ripple without significantly increasing the size and/or number of components required. The key for the secondary filter design is to choose the resonant frequency such that it is higher than the targeted crossover frequency yet well below the switching frequency and ESR zero of the bulk output capacitance. Equation 66, Equation 67, and Equation 68 can be used to determine the ESR zero as well as the resonant frequency and attenuation of the additional output filter.

Equation 66.
Equation 67.
Equation 68. GUID-20210617-CA0I-WXKK-SFXK-TDMMSGB7Q2TJ-low.png

In the event that there is peaking at high frequencies due to the output filter, a resistor can be used to dampen this peaking effect. Equation 69 and Equation 70 can be used to determine the frequency of the peaking and the value of the resistor needed to provide adequate damping.

Equation 69. GUID-20210620-CA0I-0WGW-GHCM-QKSTT2V7NL7F-low.png
Equation 70. GUID-20210617-CA0I-PDS3-CRPD-VFCQVPJVC8CX-low.png