SLUA963B June   2020  – October 2022 UCC21710-Q1 , UCC21732-Q1 , UCC5870-Q1

 

  1.   HEV/EV Traction Inverter Design Guide Using Isolated IGBT and SiC Gate Drivers
  2. 1Introduction
  3. 2HEV/EV Overview
    1. 2.1 HEV/EV Architectures
    2. 2.2 HEV/EV Traction Inverter System Architecture
    3. 2.3 HEV/EV Traction Inverter System Performance Impact
  4. 3Design of HEV/EV Traction Inverter Drive Stage
    1. 3.1  Introduction to UCC217xx-Q1
    2. 3.2  Designing a Traction Inverter Drive System Using UCC217xx-Q1
    3. 3.3  Description of Protection Features
    4. 3.4  Protection Features of UCC217xx-Q1
    5. 3.5  UCC217xx-Q1 Protection and Monitoring Features Descriptions
      1. 3.5.1 Primary and Secondary Side UVLO and OVLO
      2. 3.5.2 Over-Current (OC) and Desaturation (DESAT) Detection
      3. 3.5.3 2-Level and Soft Turn-Off
      4. 3.5.4 Power Switch Gate Voltage (VGE/VGS) Monitoring
      5. 3.5.5 Power Switch Anti-Shoot-Through
      6. 3.5.6 Integrated Internal or External Miller Clamp
      7. 3.5.7 Isolated Analog-to-PWM Channel
      8. 3.5.8 Short-Circuit Clamping
      9. 3.5.9 Active Pulldown
    6. 3.6  Introduction to UCC5870-Q1
    7. 3.7  Designing a Traction Inverter Drive System Using UCC5870-Q1
    8. 3.8  Description of Protection Features
    9. 3.9  Protection Features of UCC5870-Q1
    10. 3.10 UCC5870-Q1 Protection and Monitoring Features Descriptions
      1. 3.10.1  Primary and Secondary Side UVLO and OVLO
      2. 3.10.2  Programmable Desaturation (DESAT) Detection and Over-Current (OC)
      3. 3.10.3  Adjustable 2-Level or Soft Turn-Off
      4. 3.10.4  Active High-Voltage Clamp
      5. 3.10.5  Power Switch Gate Voltage (VGE/VGS) Monitoring
      6. 3.10.6  Gate Threshold Voltage Monitor
      7. 3.10.7  Power Switch Anti-Shoot-Through
      8. 3.10.8  Active Short Circuit (ASC)
      9. 3.10.9  Integrated Internal or External Miller Clamp
      10. 3.10.10 Isolated Analog-to-Digital Converter
        1. 3.10.10.1 Temperature Monitoring of Power Transistor
      11. 3.10.11 Short-Circuit Clamping
      12. 3.10.12 Active and Passive Pulldown
      13. 3.10.13 Thermal Shutdown and Temperature Warning of Driver IC
      14. 3.10.14 Clock Monitor and CRC
      15. 3.10.15 SPI and Register Data Protection
  5. 4Isolated Bias Supply Architecture
  6. 5Summary
  7. 6References
  8. 7Revision History

3.10.1 Primary and Secondary Side UVLO and OVLO

UVLO and OVLO functions are implemented for all three gate driver power supplies, VCC1, on the primary, and VCC2 and VEE2, on the secondary. The VCC1 UVLO ensures a valid supply is connected for the required logic interface. The UVLO/OVLO for VCC2 and VEE2 ensure valid supplies based on the type of transistor used (SiC MOSFET or IGBT). The UVLO function prevents overheating damage to the IGBTs/MOSFETs from being under-driven while OVLO is implemented to prevent gate oxide degredation (shortened lifetime) of the IGBT or MOSFET due to over-voltage when turned on.

The UCC5870-Q1 Analog Built-In Self-Test (ABIST) function runs diagnostics automatically on all under-voltage comparators monitoring VCC1, VCC2, and VEE2, and internal regulators during the power up process. During the test an over-voltage and under-voltage condition is simulated while the actual voltage rails remain unchanged, and the disturbance is not observable. A failure in this routine will set a fault.