The V_GTH Monitor function is used to measure the gate threshold voltage of the power transistor during power up, shown in Figure 3-20. The gate voltage of the power transistor is monitored in order to check the integrity of the PWM signal channel, which helps to detect any communication failure due to failed isolation barrier or broken mechanical connection. The gate voltage is compared with the input PWM (IN+) signal, where the mismatch of the two signals causes a gate voltage monitor fault condition where the a Status bit is set, and the driver output is forced to the state defined by a Configuration Register. If unmasked, nFLT1 pulls low. Blanking time relative to OUTH is used to prevent false reporting of the gate voltage monitor error during driver transitions. During 2LTOFF transitions, the blanking time starts after the 2LTOFF plateau timer expires in order to prevent false gate monitor faults during the transition. Alternatively, the gate monitor fault may also be disabled during STO and 2LTOFF. The blanking time is adjustable via SPI. Additionally, the gate monitoring function may be disabled entirely.

Figure 3-20 Gate voltage monitor