SCPS286 Data sheet

SCPS286 July 2025 TPLD2001

ADVANCE INFORMATION

7.4.4.4.3 TPLD2001_Cfg_1 Registers

Table 7-262 lists the memory-mapped registers for the TPLD2001_Cfg_1 registers. All register offset addresses not listed in Table 7-262 should be considered as reserved locations and the register contents should not be modified.

Table 7-262 TPLD2001_CFG_1 Registers

Offset	Acronym	Bit 7	Bit 6	Bit 5	Bit 4	Bit 3	Bit 2	Bit 1	Bit 0
300h	IN0_CFG	RESERVED	PULL_UP_EN	RES_SEL		RESERVED		IN_CTRL
301h	IO1_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
302h	IO2_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
303h	IO3_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
304h	IO4_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
305h	IO5_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
306h	IO6_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
307h	IO7_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
308h	IO8_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
309h	IO9_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
30Ah	IO10_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
30Bh	IO11_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
30Ch	IO12_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
30Dh	IO13_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
30Eh	IO14_CFG	OE	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
30Fh	IO15_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
310h	IO16_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
311h	IO17_CFG	RESERVED	PULL_UP_EN	RES_SEL		OUT_CTRL		IN_CTRL
320h	VIO_SEL_0	V_IN7	V_IN6	V_IN5	V_IN4	V_IN3	V_IN2	V_IN1	V_IN0
324h	LUT_FS_0	RESERVED				LUT2_3_FS	LUT2_2_FS	LUT2_1_FS	LUT2_0_FS
325h	LUT_FS_1	RESERVED		LUT3_5_FS	LUT3_4_FS	LUT3_3_FS	LUT3_2_FS	LUT3_1_FS	LUT3_0_FS
327h	LUT_FS_3	RESERVED				LUT4_3_FS	LUT4_2_FS	LUT4_1_FS	LUT4_0_FS
328h	LUT2_0_CFG	RESERVED				BIT3	BIT2	BIT1	BIT0
329h	LUT2_1_CFG	RESERVED				BIT3	BIT2	BIT1	BIT0
32Ah	LUT2_2_CFG	RESERVED				BIT3	BIT2	BIT1	BIT0
32Eh	LUT2_3_CFG0	RESERVED		PGEN_RST	RESERVED	BITS3_0
32Fh	LUT2_3_CFG1	PGEN_DATA_LSB
330h	LUT2_3_CFG2	PGEN_DATA_MSB
334h	LUT3_0_CFG	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
335h	LUT3_1_CFG	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
336h	LUT3_2_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
337h	LUT3_2_CFG1	BITS15_8
338h	LUT3_3_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
339h	LUT3_3_CFG1	BITS15_8
33Ah	LUT3_4_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
33Bh	LUT3_4_CFG1	BITS15_8
33Ch	LUT3_5_CFG0	BIT7	BITS6_4			BIT3	BIT2	BIT1	BIT0
33Dh	LUT3_5_CFG1	BITS15_8
344h	LUT4_0_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
345h	LUT4_0_CFG1	BITS15_8
346h	LUT4_1_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
347h	LUT4_1_CFG1	BITS15_8
348h	LUT4_2_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
349h	LUT4_2_CFG1	BITS15_8
34Ah	LUT4_3_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
34Bh	LUT4_3_CFG1	BITS15_8
354h	LUT3_6_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
355h	LUT3_6_CFG1	CNT_DATA
356h	LUT3_6_CFG2	CLK_SEL				MODE_SEL
357h	LUT3_6_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
358h	LUT3_6_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
359h	LUT3_7_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
35Ah	LUT3_7_CFG1	CNT_DATA
35Bh	LUT3_7_CFG2	CLK_SEL				MODE_SEL
35Ch	LUT3_7_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
35Dh	LUT3_7_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
35Eh	LUT3_8_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
35Fh	LUT3_8_CFG1	CNT_DATA
360h	LUT3_8_CFG2	CLK_SEL				MODE_SEL
361h	LUT3_8_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
362h	LUT3_8_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
363h	LUT3_9_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
364h	LUT3_9_CFG1	CNT_DATA
365h	LUT3_9_CFG2	CLK_SEL				MODE_SEL
366h	LUT3_9_CFG3	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
367h	LUT3_9_CFG4	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
372h	LUT3_10_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
373h	LUT3_10_CFG1	CNT_DATA_7:0
374h	LUT3_10_CFG2	CNT_DATA_15:8
375h	LUT3_10_CFG3	CLK_SEL				MODE_SEL
376h	LUT3_10_CFG4	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
377h	LUT3_10_CFG5	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
378h	LUT3_11_CFG0	BIT7	BIT6	BIT5	BIT4	BIT3	BIT2	BIT1	BIT0
379h	LUT3_11_CFG1	CNT_DATA_7:0
37Ah	LUT3_11_CFG2	CNT_DATA_15:8
37Bh	LUT3_11_CFG3	CLK_SEL				MODE_SEL
37Ch	LUT3_11_CFG4	RESERVED		RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
37Dh	LUT3_11_CFG5	RESERVED			LDC_FS	LDC_CMX_IN_SEL		LDC_CMX_MODE
37Eh	CNT6_FSM0_CFG0	CNT_DATA
37Fh	CNT6_FSM0_CFG1	CLK_SEL				MODE_SEL
380h	CNT6_FSM0_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
381h	CNT7_FSM1_CFG0	CNT_DATA
382h	CNT7_FSM1_CFG1	CLK_SEL				MODE_SEL
383h	CNT7_FSM1_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
384h	CNT8_FSM2_CFG0	CNT_DATA
385h	CNT8_FSM2_CFG1	CLK_SEL				MODE_SEL
386h	CNT8_FSM2_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
387h	CNT9_FSM3_CFG0	CNT_DATA
388h	CNT9_FSM3_CFG1	CLK_SEL				MODE_SEL
389h	CNT9_FSM3_CFG2	UP_SYNC	KEEP_SYNC	RST_SYNC	RESERVED	CNT_INIT		OUT_POL	DLY_EDET
38Ah	PWM_GEN0_CFG	RESERVED				TDB_SEL		OUTP_POL	OUTN_POL
38Bh	PWM_GEN1_CFG	RESERVED				TDB_SEL		OUTP_POL	OUTN_POL
38Ch	PWM_GEN2_CFG	RESERVED				TDB_SEL		OUTP_POL	OUTN_POL
38Dh	PWM_GEN3_CFG	RESERVED				TDB_SEL		OUTP_POL	OUTN_POL
38Eh	PWM_SRC_CFG	PWM_GEN3_DATA_SEL		PWM_GEN2_DATA_SEL		PWM_GEN1_DATA_SEL		PWM_GEN0_DATA_SEL
38Fh	SM_CFG0	RESERVED	SM_S1_IN0			RESERVED	SM_S0_IN0
390h	SM_CFG1	RESERVED	SM_S1_IN1			RESERVED	SM_S0_IN1
391h	SM_CFG2	RESERVED	SM_S1_IN2			RESERVED	SM_S0_IN2
392h	SM_CFG3	RESERVED	SM_S3_IN0			RESERVED	SM_S2_IN0
393h	SM_CFG4	RESERVED	SM_S3_IN1			RESERVED	SM_S2_IN1
394h	SM_CFG5	RESERVED	SM_S3_IN2			RESERVED	SM_S2_IN2
395h	SM_CFG6	RESERVED	SM_S5_IN0			RESERVED	SM_S4_IN0
396h	SM_CFG7	RESERVED	SM_S5_IN1			RESERVED	SM_S4_IN1
397h	SM_CFG8	RESERVED	SM_S5_IN2			RESERVED	SM_S4_IN2
398h	SM_CFG9	RESERVED	SM_S7_IN0			RESERVED	SM_S6_IN0
399h	SM_CFG10	RESERVED	SM_S7_IN1			RESERVED	SM_S6_IN1
39Ah	SM_CFG11	SM_SYNC_EN	SM_S7_IN2			RESERVED	SM_S6_IN2
3A7h	SM_CFG12	SM_CLK_SEL				SM_MODE	SM_INIT_STATE
3A8h	SM_CFG13	S0_OUT_CFG
3A9h	SM_CFG14	S1_OUT_CFG
3AAh	SM_CFG15	S2_OUT_CFG
3ABh	SM_CFG16	S3_OUT_CFG
3ACh	SM_CFG17	S4_OUT_CFG
3ADh	SM_CFG18	S5_OUT_CFG
3AEh	SM_CFG19	S6_OUT_CFG
3AFh	SM_CFG20	S7_OUT_CFG
3B8h	WDT_CFG0	WDT_TIMEOUT_DATA
3B9h	WDT_CFG1	WDT_OUT_DATA
3BAh	WDT_CFG2	WDT_CLK_SEL				RESERVED		WDT_100X_EN	WDT_EN_SEL
3BBh	PFLT0_CFG	RESERVED		PFLT_DLY_SEL		PFLT_POL	RESERVED	PFLT_EDGE_SEL
3BCh	PFLT1_CFG	RESERVED		PFLT_DLY_SEL		PFLT_POL	RESERVED	PFLT_EDGE_SEL
3BDh	FILT_CFG	RESERVED				FLT_POL	OTP_SPARE	FLT_EDGE_SEL
3BEh	OSC0_CFG0	RESERVED	CTRL_SRC	CTRL_SEL	SRC_SEL	PDIV		RESERVED	PWR_MODE
3BFh	OSC0_CFG1	OUT1_EN	OUT1_DIV			OUT0_EN	OUT0_DIV
3C0h	OSC1_CFG0	RESERVED	CTRL_SRC	CTRL_SEL	SRC_SEL	PDIV		RESERVED	PWR_MODE
3C1h	OSC1_CFG1	OUT1_EN	OUT1_DIV			OUT0_EN	OUT0_DIV
3C2h	OSC2_CFG0	SU_DLY	CTRL_SRC	CTRL_SEL	SRC_SEL	PDIV		RESERVED	PWR_MODE
3C3h	OSC2_CFG1	RESERVED				OUT_EN	OUT_DIV
3C6h	ACMP0_CFG0	BW_SEL		INP_SEL		GAIN_SEL		HYS_SEL
3C7h	ACMP0_CFG1	RESERVED		VREF_SEL
3C8h	ACMP1_CFG0	BW_SEL		INP_SEL		GAIN_SEL		HYS_SEL
3C9h	ACMP1_CFG1	RESERVED		VREF_SEL
3CAh	ACMP2_CFG0	BW_SEL		INP_SEL		GAIN_SEL		HYS_SEL
3CBh	ACMP2_CFG1	RESERVED		VREF_SEL
3CCh	ACMP3_CFG0	BW_SEL		INP_SEL		GAIN_SEL		HYS_SEL
3CDh	ACMP3_CFG1	RESERVED		VREF_SEL
3CFh	MCACMP_CFG0	TS_INP_EN	VCC_INP_EN	SYNC_EN	MCS_MODE	CH_EN		RESERVED	MCS_EN
3D0h	MCACMP_CFG1	BW_SEL		RESERVED			EDGE_SEL	MCS_CLK_SEL
3D1h	MCACMP_CH0_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3D2h	MCACMP_CH0_CFG1	CH_VREF_SEL		VREF_SEL
3D3h	MCACMP_CH0_CFG2	RESERVED		VREF_SEL1
3D6h	MCACMP_CH1_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3D7h	MCACMP_CH1_CFG1	CH_VREF_SEL		VREF_SEL
3D8h	MCACMP_CH1_CFG2	RESERVED		VREF_SEL1
3DBh	MCACMP_CH2_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3DCh	MCACMP_CH2_CFG1	CH_VREF_SEL		VREF_SEL
3DDh	MCACMP_CH2_CFG2	RESERVED		VREF_SEL1
3E0h	MCACMP_CH3_CFG0	RESERVED	RST_EN	INP_SEL		GAIN_SEL		HYS_SEL
3E1h	MCACMP_CH3_CFG1	CH_VREF_SEL		VREF_SEL
3E2h	MCACMP_CH3_CFG2	RESERVED		VREF_SEL1
3E5h	AMUX0_CFG	RESERVED							AMUX_EN
3E6h	AMUX1_CFG	RESERVED							AMUX_EN
3F2h	SER_COMM_CFG0	I2C_ADDR_SRC_SEL				I2C_IO_LAT	I2C_RST_EN	I2C_EN	SPI_EN
3F3h	SER_COMM_CFG1	I2C_ADDR_MSB				I2C_ADDR_LSB			RESERVED
3F7h	MISC_CFG0	GPIO_QC	CFG_RD_LCK	CFG_WR_LCK	OTP_WR_LCK	USER_LCK		RESERVED
3FAh	DEVICE_ID4	DEVICE_ID4
3FBh	DEVICE_ID5	DEVICE_ID5
3FCh	DEVICE_ID6	DEVICE_ID6
3FDh	DEVICE_ID7	DEVICE_ID7
3FEh	CRC_LSB	CRC_LSB
3FFh	CRC_MSB	CRC_MSB

Complex bit access types are encoded to fit into small table cells. Table 7-263 shows the codes that are used for access types in this section.

Table 7-263 TPLD2001_Cfg_1 Access Type Codes

Access Type	Code	Description
Read Type
R	R	Read
Write Type
W	W	Write
Reset or Default Value
-n		Value after reset or the default value

4.4.3.1 IN0_CFG Register (Offset = 300h) [Reset = XXh]

IN0_CFG is shown in Table 7-264.

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GPI configuration

Table 7-264 IN0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	RESERVED	R	0h	Reserved
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

4.4.3.2 IO1_CFG Register (Offset = 301h) [Reset = XXh]

IO1_CFG is shown in Table 7-265.

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GPIO1 configuration

Table 7-265 IO1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.3 IO2_CFG Register (Offset = 302h) [Reset = XXh]

IO2_CFG is shown in Table 7-266.

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GPIO2 configuration

Table 7-266 IO2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.4 IO3_CFG Register (Offset = 303h) [Reset = XXh]

IO3_CFG is shown in Table 7-267.

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GPIO3 configuration

Table 7-267 IO3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.5 IO4_CFG Register (Offset = 304h) [Reset = X0h]

IO4_CFG is shown in Table 7-268.

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GPIO4 configuration

Table 7-268 IO4_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.6 IO5_CFG Register (Offset = 305h) [Reset = X0h]

IO5_CFG is shown in Table 7-269.

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GPIO5 configuration

Table 7-269 IO5_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

4.4.3.7 IO6_CFG Register (Offset = 306h) [Reset = X0h]

IO6_CFG is shown in Table 7-270.

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GPIO6 configuration

Table 7-270 IO6_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 4X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

4.4.3.8 IO7_CFG Register (Offset = 307h) [Reset = X0h]

IO7_CFG is shown in Table 7-271.

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GPIO7 configuration

Table 7-271 IO7_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 4X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

4.4.3.9 IO8_CFG Register (Offset = 308h) [Reset = X0h]

IO8_CFG is shown in Table 7-272.

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GPIO8 configuration

Table 7-272 IO8_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Reserved

4.4.3.10 IO9_CFG Register (Offset = 309h) [Reset = X0h]

IO9_CFG is shown in Table 7-273.

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GPIO9 configuration

Table 7-273 IO9_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.11 IO10_CFG Register (Offset = 30Ah) [Reset = XXh]

IO10_CFG is shown in Table 7-274.

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GPIO10 Configuration

Table 7-274 IO10_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.12 IO11_CFG Register (Offset = 30Bh) [Reset = XXh]

IO11_CFG is shown in Table 7-275.

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GPIO11 Configuration

Table 7-275 IO11_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.13 IO12_CFG Register (Offset = 30Ch) [Reset = XXh]

IO12_CFG is shown in Table 7-276.

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GPIO12 Configuration

Table 7-276 IO12_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.14 IO13_CFG Register (Offset = 30Dh) [Reset = XXh]

IO13_CFG is shown in Table 7-277.

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GPIO13 Configuration

Table 7-277 IO13_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.15 IO14_CFG Register (Offset = 30Eh) [Reset = X0h]

IO14_CFG is shown in Table 7-278.

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GPIO14 Configuration

Table 7-278 IO14_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OE	R/W	0h	0h = Input 1h = Output
6	PULL_UP_EN	R/W	0h	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	0h	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.16 IO15_CFG Register (Offset = 30Fh) [Reset = XXh]

IO15_CFG is shown in Table 7-279.

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GPIO15 Configuration

Table 7-279 IO15_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.17 IO16_CFG Register (Offset = 310h) [Reset = XXh]

IO16_CFG is shown in Table 7-280.

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GPIO16 Configuration

Table 7-280 IO16_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.18 IO17_CFG Register (Offset = 311h) [Reset = XXh]

IO17_CFG is shown in Table 7-281.

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GPIO17 Configuration

Table 7-281 IO17_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	PULL_UP_EN	R/W	Xh	0h = Pull down 1h = Pull up
5:4	RES_SEL	R/W	Xh	0h = Floating 1h = 10k Ω 2h = 100k Ω 3h = 1M Ω
3:2	OUT_CTRL	R/W	Xh	0h = Push-pull 1X 1h = Push-pull 2X 2h = Open-drain NMOS 1X 3h = Open-drain NMOS 2X
1:0	IN_CTRL	R/W	Xh	0h = Digital input without Schmitt Trigger 1h = Digital input with Schmitt Trigger 2h = Low voltage digital input 3h = Analog I/O

4.4.3.19 VIO_SEL_0 Register (Offset = 320h) [Reset = X0h]

VIO_SEL_0 is shown in Table 7-282.

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IO8 to IO1 virtual IO select

Table 7-282 VIO_SEL_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	V_IN7	R/W	0h	0h = IO8 1h = V_IN7
6	V_IN6	R/W	0h	0h = IO7 1h = V_IN6
5	V_IN5	R/W	0h	0h = IO6 1h = V_IN5
4	V_IN4	R/W	0h	0h = IO5 1h = V_IN4
3	V_IN3	R/W	Xh	0h = IO4 1h = V_IN3
2	V_IN2	R/W	Xh	0h = IO3 1h = V_IN2
1	V_IN1	R/W	Xh	0h = IO2 1h = V_IN1
0	V_IN0	R/W	Xh	0h = IO1 1h = V_IN0

4.4.3.20 LUT_FS_0 Register (Offset = 324h) [Reset = 0Xh]

LUT_FS_0 is shown in Table 7-283.

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LUT2_3 to LUT2_0 function select

Table 7-283 LUT_FS_0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	LUT2_3_FS	R/W	Xh	0h = LUT 1h = PGEN
2	LUT2_2_FS	R/W	Xh	0h = LUT 1h = DFF
1	LUT2_1_FS	R/W	Xh	0h = LUT 1h = DFF
0	LUT2_0_FS	R/W	Xh	0h = LUT 1h = DFF

4.4.3.21 LUT_FS_1 Register (Offset = 325h) [Reset = XXh]

LUT_FS_1 is shown in Table 7-284.

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LUT3_5 to LUT3_0 function select

Table 7-284 LUT_FS_1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	LUT3_5_FS	R/W	Xh	0h = LUT 1h = DFF/SR
4	LUT3_4_FS	R/W	Xh	0h = LUT 1h = DFF/SR
3	LUT3_3_FS	R/W	Xh	0h = LUT 1h = DFF/SR
2	LUT3_2_FS	R/W	Xh	0h = LUT 1h = DFF/SR
1	LUT3_1_FS	R/W	Xh	0h = LUT 1h = DFF
0	LUT3_0_FS	R/W	Xh	0h = LUT 1h = DFF

4.4.3.22 LUT_FS_3 Register (Offset = 327h) [Reset = 0Xh]

LUT_FS_3 is shown in Table 7-285.

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LUT4_3 to LUT4_0 function select

Table 7-285 LUT_FS_3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	LUT4_3_FS	R/W	Xh	0h = LUT 1h = DFF
2	LUT4_2_FS	R/W	Xh	0h = LUT 1h = DFF
1	LUT4_1_FS	R/W	Xh	0h = LUT 1h = DFF
0	LUT4_0_FS	R/W	Xh	0h = LUT 1h = DFF

4.4.3.23 LUT2_0_CFG Register (Offset = 328h) [Reset = X0h]

LUT2_0_CFG is shown in Table 7-286.

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LUT2_0 / DFF0 configuration

Table 7-286 LUT2_0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	BIT3	R/W	Xh	LUT2[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT2[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT2[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT2[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.24 LUT2_1_CFG Register (Offset = 329h) [Reset = X0h]

LUT2_1_CFG is shown in Table 7-287.

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LUT2_1 / DFF1 configuration

Table 7-287 LUT2_1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	BIT3	R/W	Xh	LUT2[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT2[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT2[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT2[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.25 LUT2_2_CFG Register (Offset = 32Ah) [Reset = X0h]

LUT2_2_CFG is shown in Table 7-288.

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LUT2_2 / DFF2 configuration

Table 7-288 LUT2_2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	BIT3	R/W	Xh	LUT2[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT2[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT2[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT2[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.26 LUT2_3_CFG0 Register (Offset = 32Eh) [Reset = XXh]

LUT2_3_CFG0 is shown in Table 7-289.

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LUT2_3 / PGEN configuration 0

Table 7-289 LUT2_3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	PGEN_RST	R/W	Xh	OTP_SPARE or PGEN RST LVL 0h = Low 1h = High
4	RESERVED	R	0h	Reserved
3:0	BITS3_0	R/W	Xh	LUT2[3:0] or PGEN SIZE 0h = 1 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8 8h = 9 9h = 10 Ah = 11 Bh = 12 Ch = 13 Dh = 14 Eh = 15 Fh = 16

4.4.3.27 LUT2_3_CFG1 Register (Offset = 32Fh) [Reset = X0h]

LUT2_3_CFG1 is shown in Table 7-290.

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PGEN configuration 1

Table 7-290 LUT2_3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_DATA_LSB	R/W	Xh	PGEN_DATA[7:0]

4.4.3.28 LUT2_3_CFG2 Register (Offset = 330h) [Reset = X0h]

LUT2_3_CFG2 is shown in Table 7-291.

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PGEN configuration 2

Table 7-291 LUT2_3_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	PGEN_DATA_MSB	R/W	Xh	PGEN_DATA[15:8]

4.4.3.29 LUT3_0_CFG Register (Offset = 334h) [Reset = X0h]

LUT3_0_CFG is shown in Table 7-292.

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LUT3_0 / DFF3 configuration

Table 7-292 LUT3_0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.30 LUT3_1_CFG Register (Offset = 335h) [Reset = X0h]

LUT3_1_CFG is shown in Table 7-293.

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LUT3_1 / DFF4 configuration

Table 7-293 LUT3_1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.31 LUT3_2_CFG0 Register (Offset = 336h) [Reset = X0h]

LUT3_2_CFG0 is shown in Table 7-294.

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LUT3_2 / DFF5 / SR0 configuration 0

Table 7-294 LUT3_2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.32 LUT3_2_CFG1 Register (Offset = 337h) [Reset = X0h]

LUT3_2_CFG1 is shown in Table 7-295.

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LUT3_2 / DFF5 / SR0 configuration 1

Table 7-295 LUT3_2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	DFF / SR INIT VAL

4.4.3.33 LUT3_3_CFG0 Register (Offset = 338h) [Reset = X0h]

LUT3_3_CFG0 is shown in Table 7-296.

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LUT3_3 / DFF6 / SR1 configuration 0

Table 7-296 LUT3_3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.34 LUT3_3_CFG1 Register (Offset = 339h) [Reset = X0h]

LUT3_3_CFG1 is shown in Table 7-297.

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LUT3_3 / DFF6 / SR1 configuration 1

Table 7-297 LUT3_3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	DFF / SR INIT VAL

4.4.3.35 LUT3_4_CFG0 Register (Offset = 33Ah) [Reset = X0h]

LUT3_4_CFG0 is shown in Table 7-298.

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LUT3_4 / DFF7 / SR2 configuration 0

Table 7-298 LUT3_4_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.36 LUT3_4_CFG1 Register (Offset = 33Bh) [Reset = X0h]

LUT3_4_CFG1 is shown in Table 7-299.

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LUT3_4 / DFF7 / SR2 configuration 1

Table 7-299 LUT3_4_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	DFF / SR INIT VAL

4.4.3.37 LUT3_5_CFG0 Register (Offset = 33Ch) [Reset = X0h]

LUT3_5_CFG0 is shown in Table 7-300.

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LUT3_5 / DFF8 / SR3 configuration 0

Table 7-300 LUT3_5_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6:4	BITS6_4	R/W	0h	LUT3[6:4] or SR SIZE 0h = 1 (DFF) 1h = 2 2h = 3 3h = 4 4h = 5 5h = 6 6h = 7 7h = 8
3	BIT3	R/W	Xh	LUT3[3] or DFF / SR RST LVL 0h = Low 1h = High
2	BIT2	R/W	Xh	LUT3[2] or DFF / SR RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
1	BIT1	R/W	Xh	LUT3[1] or DFF / SR OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.38 LUT3_5_CFG1 Register (Offset = 33Dh) [Reset = X0h]

LUT3_5_CFG1 is shown in Table 7-301.

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LUT3_5 / DFF8 / SR3 configuration 1

Table 7-301 LUT3_5_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	DFF / SR INIT VAL

4.4.3.39 LUT4_0_CFG0 Register (Offset = 344h) [Reset = X0h]

LUT4_0_CFG0 is shown in Table 7-302.

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LUT4_0 / DFF15 configuration 0

Table 7-302 LUT4_0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT4[7]
6	BIT6	R/W	0h	LUT4[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT4[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT4[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT4[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT4[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT4[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT4[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.40 LUT4_0_CFG1 Register (Offset = 345h) [Reset = X0h]

LUT4_0_CFG1 is shown in Table 7-303.

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LUT4_0 / DFF15 configuration 1

Table 7-303 LUT4_0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	LUT4[15:8]

4.4.3.41 LUT4_1_CFG0 Register (Offset = 346h) [Reset = X0h]

LUT4_1_CFG0 is shown in Table 7-304.

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LUT4_1 / DFF16 configuration 0

Table 7-304 LUT4_1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT4[7]
6	BIT6	R/W	0h	LUT4[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT4[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT4[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT4[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT4[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT4[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT4[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.42 LUT4_1_CFG1 Register (Offset = 347h) [Reset = X0h]

LUT4_1_CFG1 is shown in Table 7-305.

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LUT4_1 / DFF16 configuration 1

Table 7-305 LUT4_1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	LUT4[15:8]

4.4.3.43 LUT4_2_CFG0 Register (Offset = 348h) [Reset = X0h]

LUT4_2_CFG0 is shown in Table 7-306.

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LUT4_2 / DFF17 configuration 0

Table 7-306 LUT4_2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT4[7]
6	BIT6	R/W	0h	LUT4[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT4[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT4[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT4[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT4[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT4[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT4[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.44 LUT4_2_CFG1 Register (Offset = 349h) [Reset = X0h]

LUT4_2_CFG1 is shown in Table 7-307.

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LUT4_2 / DFF17 configuration 1

Table 7-307 LUT4_2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	LUT4[15:8]

4.4.3.45 LUT4_3_CFG0 Register (Offset = 34Ah) [Reset = X0h]

LUT4_3_CFG0 is shown in Table 7-308.

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LUT4_3 / DFF18 configuration 0

Table 7-308 LUT4_3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT4[7]
6	BIT6	R/W	0h	LUT4[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT4[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT4[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT4[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT4[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT4[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT4[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.46 LUT4_3_CFG1 Register (Offset = 34Bh) [Reset = X0h]

LUT4_3_CFG1 is shown in Table 7-309.

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LUT4_3 / DFF18 configuration 1

Table 7-309 LUT4_3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	BITS15_8	R/W	Xh	LUT4[15:8]

4.4.3.47 LUT3_6_CFG0 Register (Offset = 354h) [Reset = X0h]

LUT3_6_CFG0 is shown in Table 7-310.

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LDC0 configuration 0

Table 7-310 LUT3_6_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.48 LUT3_6_CFG1 Register (Offset = 355h) [Reset = X0h]

LUT3_6_CFG1 is shown in Table 7-311.

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LDC0 configuration 1

Table 7-311 LUT3_6_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.49 LUT3_6_CFG2 Register (Offset = 356h) [Reset = X0h]

LUT3_6_CFG2 is shown in Table 7-312.

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LDC0 configuration 2

Table 7-312 LUT3_6_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.50 LUT3_6_CFG3 Register (Offset = 357h) [Reset = X0h]

LUT3_6_CFG3 is shown in Table 7-313.

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LDC0 configuration 3

Table 7-313 LUT3_6_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.51 LUT3_6_CFG4 Register (Offset = 358h) [Reset = XXh]

LUT3_6_CFG4 is shown in Table 7-314.

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LDC0 configuration 4

Table 7-314 LUT3_6_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

4.4.3.52 LUT3_7_CFG0 Register (Offset = 359h) [Reset = X0h]

LUT3_7_CFG0 is shown in Table 7-315.

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LDC1 configuration 0

Table 7-315 LUT3_7_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.53 LUT3_7_CFG1 Register (Offset = 35Ah) [Reset = X0h]

LUT3_7_CFG1 is shown in Table 7-316.

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LDC1 configuration 1

Table 7-316 LUT3_7_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.54 LUT3_7_CFG2 Register (Offset = 35Bh) [Reset = X0h]

LUT3_7_CFG2 is shown in Table 7-317.

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LDC1 configuration 2

Table 7-317 LUT3_7_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.55 LUT3_7_CFG3 Register (Offset = 35Ch) [Reset = X0h]

LUT3_7_CFG3 is shown in Table 7-318.

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LDC1 configuration 3

Table 7-318 LUT3_7_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.56 LUT3_7_CFG4 Register (Offset = 35Dh) [Reset = XXh]

LUT3_7_CFG4 is shown in Table 7-319.

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LDC1 configuration 4

Table 7-319 LUT3_7_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

4.4.3.57 LUT3_8_CFG0 Register (Offset = 35Eh) [Reset = X0h]

LUT3_8_CFG0 is shown in Table 7-320.

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LDC2 configuration 0

Table 7-320 LUT3_8_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.58 LUT3_8_CFG1 Register (Offset = 35Fh) [Reset = X0h]

LUT3_8_CFG1 is shown in Table 7-321.

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LDC2 configuration 1

Table 7-321 LUT3_8_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.59 LUT3_8_CFG2 Register (Offset = 360h) [Reset = X0h]

LUT3_8_CFG2 is shown in Table 7-322.

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LDC2 configuration 2

Table 7-322 LUT3_8_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.60 LUT3_8_CFG3 Register (Offset = 361h) [Reset = X0h]

LUT3_8_CFG3 is shown in Table 7-323.

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LDC2 configuration 3

Table 7-323 LUT3_8_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.61 LUT3_8_CFG4 Register (Offset = 362h) [Reset = XXh]

LUT3_8_CFG4 is shown in Table 7-324.

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LDC2 configuration 4

Table 7-324 LUT3_8_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

4.4.3.62 LUT3_9_CFG0 Register (Offset = 363h) [Reset = X0h]

LUT3_9_CFG0 is shown in Table 7-325.

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LDC3 configuration 0

Table 7-325 LUT3_9_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.63 LUT3_9_CFG1 Register (Offset = 364h) [Reset = X0h]

LUT3_9_CFG1 is shown in Table 7-326.

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LDC3 configuration 1

Table 7-326 LUT3_9_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.64 LUT3_9_CFG2 Register (Offset = 365h) [Reset = X0h]

LUT3_9_CFG2 is shown in Table 7-327.

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LDC3 configuration 2

Table 7-327 LUT3_9_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.65 LUT3_9_CFG3 Register (Offset = 366h) [Reset = X0h]

LUT3_9_CFG3 is shown in Table 7-328.

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LDC3 configuration 3

Table 7-328 LUT3_9_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.66 LUT3_9_CFG4 Register (Offset = 367h) [Reset = XXh]

LUT3_9_CFG4 is shown in Table 7-329.

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LDC3 configuration 4

Table 7-329 LUT3_9_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

4.4.3.67 LUT3_10_CFG0 Register (Offset = 372h) [Reset = X0h]

LUT3_10_CFG0 is shown in Table 7-330.

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LDC4 configuration 0

Table 7-330 LUT3_10_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.68 LUT3_10_CFG1 Register (Offset = 373h) [Reset = X0h]

LUT3_10_CFG1 is shown in Table 7-331.

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LDC4 configuration 1

Table 7-331 LUT3_10_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA_7:0	R/W	Xh	CNT DATA[7:0]

4.4.3.69 LUT3_10_CFG2 Register (Offset = 374h) [Reset = X0h]

LUT3_10_CFG2 is shown in Table 7-332.

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LDC4 configuration 2

Table 7-332 LUT3_10_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA_15:8	R/W	Xh	CNT_DATA[15:8]

4.4.3.70 LUT3_10_CFG3 Register (Offset = 375h) [Reset = X0h]

LUT3_10_CFG3 is shown in Table 7-333.

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LDC4 configuration 3

Table 7-333 LUT3_10_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.71 LUT3_10_CFG4 Register (Offset = 376h) [Reset = X0h]

LUT3_10_CFG4 is shown in Table 7-334.

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LDC4 configuration 4

Table 7-334 LUT3_10_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.72 LUT3_10_CFG5 Register (Offset = 377h) [Reset = XXh]

LUT3_10_CFG5 is shown in Table 7-335.

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LDC4 configuration 5

Table 7-335 LUT3_10_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

4.4.3.73 LUT3_11_CFG0 Register (Offset = 378h) [Reset = X0h]

LUT3_11_CFG0 is shown in Table 7-336.

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LDC5 configuration 0

Table 7-336 LUT3_11_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	BIT7	R/W	0h	LUT3[7]
6	BIT6	R/W	0h	LUT3[6] or DFF NUM SEL 0h = 1-DFF 1h = 2-DFF
5	BIT5	R/W	0h	LUT3[5] or DFF RST LVL 0h = Low 1h = High
4	BIT4	R/W	0h	LUT3[4] or DFF RST / SET SEL 0h = Reset (CLRZ) 1h = Set (PREZ)
3	BIT3	R/W	Xh	LUT3[3] or DFF CLK POL 0h = Non-inverted clock 1h = Inverted clock
2	BIT2	R/W	Xh	LUT3[2] or DFF INIT VAL 0h = Low 1h = High
1	BIT1	R/W	Xh	LUT3[1] or DFF OUT POL 0h = Non-inverted output 1h = Inverted output
0	BIT0	R/W	Xh	LUT3[0] or DFF / LAT SEL 0h = DFF function 1h = LATCH function

4.4.3.74 LUT3_11_CFG1 Register (Offset = 379h) [Reset = X0h]

LUT3_11_CFG1 is shown in Table 7-337.

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LDC5 configuration 1

Table 7-337 LUT3_11_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA_7:0	R/W	Xh	CNT DATA[7:0]

4.4.3.75 LUT3_11_CFG2 Register (Offset = 37Ah) [Reset = X0h]

LUT3_11_CFG2 is shown in Table 7-338.

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LDC5 configuration 2

Table 7-338 LUT3_11_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA_15:8	R/W	Xh	CNT_DATA[15:8]

4.4.3.76 LUT3_11_CFG3 Register (Offset = 37Bh) [Reset = X0h]

LUT3_11_CFG3 is shown in Table 7-339.

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LDC5 configuration 3

Table 7-339 LUT3_11_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.77 LUT3_11_CFG4 Register (Offset = 37Ch) [Reset = X0h]

LUT3_11_CFG4 is shown in Table 7-340.

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LDC5 configuration 4

Table 7-340 LUT3_11_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.78 LUT3_11_CFG5 Register (Offset = 37Dh) [Reset = XXh]

LUT3_11_CFG5 is shown in Table 7-341.

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LDC5 configuration 5

Table 7-341 LUT3_11_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:5	RESERVED	R	0h	Reserved
4	LDC_FS	R/W	Xh	LUT3 / DFF function select 0h = LUT 1h = DFF
3:2	LDC_CMX_IN_SEL	R/W	Xh	LUT3 / DFF input routing select 0h = CNT OUT to LUT IN2 / DFF RST IN 1h = CNT OUT to LUT IN1 / DFF D IN 2h = CNT OUT to LUT IN0 / DFF CLK IN 3h = Reserved
1:0	LDC_CMX_MODE	R/W	Xh	LUT3 / DFF + CNT mode select 0h = LUT / DFF only 1h = CNT only 2h = CNT OUT to LUT / DFF IN 3h = LUT / DFF OUT to CNT IN

4.4.3.79 CNT6_FSM0_CFG0 Register (Offset = 37Eh) [Reset = X0h]

CNT6_FSM0_CFG0 is shown in Table 7-342.

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Table 7-342 CNT6_FSM0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.80 CNT6_FSM0_CFG1 Register (Offset = 37Fh) [Reset = X0h]

CNT6_FSM0_CFG1 is shown in Table 7-343.

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Table 7-343 CNT6_FSM0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.81 CNT6_FSM0_CFG2 Register (Offset = 380h) [Reset = 0Xh]

CNT6_FSM0_CFG2 is shown in Table 7-344.

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Table 7-344 CNT6_FSM0_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.82 CNT7_FSM1_CFG0 Register (Offset = 381h) [Reset = X0h]

CNT7_FSM1_CFG0 is shown in Table 7-345.

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Table 7-345 CNT7_FSM1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.83 CNT7_FSM1_CFG1 Register (Offset = 382h) [Reset = X0h]

CNT7_FSM1_CFG1 is shown in Table 7-346.

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Table 7-346 CNT7_FSM1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.84 CNT7_FSM1_CFG2 Register (Offset = 383h) [Reset = 0Xh]

CNT7_FSM1_CFG2 is shown in Table 7-347.

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Table 7-347 CNT7_FSM1_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.85 CNT8_FSM2_CFG0 Register (Offset = 384h) [Reset = X0h]

CNT8_FSM2_CFG0 is shown in Table 7-348.

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Table 7-348 CNT8_FSM2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.86 CNT8_FSM2_CFG1 Register (Offset = 385h) [Reset = X0h]

CNT8_FSM2_CFG1 is shown in Table 7-349.

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Table 7-349 CNT8_FSM2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.87 CNT8_FSM2_CFG2 Register (Offset = 386h) [Reset = 0Xh]

CNT8_FSM2_CFG2 is shown in Table 7-350.

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Table 7-350 CNT8_FSM2_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.88 CNT9_FSM3_CFG0 Register (Offset = 387h) [Reset = X0h]

CNT9_FSM3_CFG0 is shown in Table 7-351.

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Table 7-351 CNT9_FSM3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CNT_DATA	R/W	Xh	CNT DATA

4.4.3.89 CNT9_FSM3_CFG1 Register (Offset = 388h) [Reset = X0h]

CNT9_FSM3_CFG1 is shown in Table 7-352.

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Table 7-352 CNT9_FSM3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	CLK_SEL	R/W	0h	CNT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:0	MODE_SEL	R/W	Xh	CNT MODE and EDGE SEL 0h = Delay / Both edge 1h = Delay / Falling edge 2h = Delay / Rising edge 3h = One-shot / Both edge 4h = One-shot / Falling edge 5h = One-shot / Rising edge 6h = Frequency detect / Both edge 7h = Frequency detect / Falling edge 8h = Frequency detect / Rising edge 9h = Edge detect / Both edge Ah = Edge detect / Falling edge Bh = Edge detect / Rising edge Ch = Counter / Both edge Dh = Counter / Falling edge Eh = Counter / Rising edge Fh = Counter / High-level reset

4.4.3.90 CNT9_FSM3_CFG2 Register (Offset = 389h) [Reset = 0Xh]

CNT9_FSM3_CFG2 is shown in Table 7-353.

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Table 7-353 CNT9_FSM3_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	UP_SYNC	R/W	0h	FSM UP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
6	KEEP_SYNC	R/W	0h	FSM KEEP SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
5	RST_SYNC	R/W	0h	CNT RST SYNC bypass option 0h = 2-DFF sync 1h = Bypass 2-DFF
4	RESERVED	R	0h	Reserved
3:2	CNT_INIT	R/W	Xh	CNT INIT VAL 0h = Bypass initial 1h = Initial Low 2h = Initial High 3h = Initial High (Reserved)
1	OUT_POL	R/W	Xh	CNT OUT POL 0h = Non-inverted 1h = Inverted
0	DLY_EDET	R/W	Xh	DLY EDGE DETECT option 0h = Delay function 1h = Enable edge detect on delay function

4.4.3.91 PWM_GEN0_CFG Register (Offset = 38Ah) [Reset = X0h]

PWM_GEN0_CFG is shown in Table 7-354.

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Table 7-354 PWM_GEN0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

4.4.3.92 PWM_GEN1_CFG Register (Offset = 38Bh) [Reset = X0h]

PWM_GEN1_CFG is shown in Table 7-355.

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Table 7-355 PWM_GEN1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

4.4.3.93 PWM_GEN2_CFG Register (Offset = 38Ch) [Reset = X0h]

PWM_GEN2_CFG is shown in Table 7-356.

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Table 7-356 PWM_GEN2_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

4.4.3.94 PWM_GEN3_CFG Register (Offset = 38Dh) [Reset = X0h]

PWM_GEN3_CFG is shown in Table 7-357.

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Table 7-357 PWM_GEN3_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3:2	TDB_SEL	R/W	Xh	PWM Deadband time select 0h = 0 CLKs 1h = 1 CLK 2h = 2 CLKs 3h = 5 CLKs
1	OUTP_POL	R/W	Xh	PWM OUT1 POL 0h = Non-inverted output 1h = Inverted output
0	OUTN_POL	R/W	Xh	PWM OUT0 POL 0h = Non-inverted output 1h = Inverted output

4.4.3.95 PWM_SRC_CFG Register (Offset = 38Eh) [Reset = X0h]

PWM_SRC_CFG is shown in Table 7-358.

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Table 7-358 PWM_SRC_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	PWM_GEN3_DATA_SEL	R/W	0h	PWM3 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3
5:4	PWM_GEN2_DATA_SEL	R/W	0h	PWM2 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3
3:2	PWM_GEN1_DATA_SEL	R/W	Xh	PWM1 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3
1:0	PWM_GEN0_DATA_SEL	R/W	Xh	PWM0 DATA source select 0h = FSM0 1h = FSM1 2h = FSM2 3h = FSM3

4.4.3.96 SM_CFG0 Register (Offset = 38Fh) [Reset = XXh]

SM_CFG0 is shown in Table 7-359.

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Table 7-359 SM_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S1_IN0	R/W	Xh	STATE1 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S0_IN0	R/W	Xh	STATE0 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.97 SM_CFG1 Register (Offset = 390h) [Reset = XXh]

SM_CFG1 is shown in Table 7-360.

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Table 7-360 SM_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S1_IN1	R/W	Xh	STATE1 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S0_IN1	R/W	Xh	STATE0 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.98 SM_CFG2 Register (Offset = 391h) [Reset = XXh]

SM_CFG2 is shown in Table 7-361.

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Table 7-361 SM_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S1_IN2	R/W	Xh	STATE1 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S0_IN2	R/W	Xh	STATE0 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.99 SM_CFG3 Register (Offset = 392h) [Reset = XXh]

SM_CFG3 is shown in Table 7-362.

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Table 7-362 SM_CFG3 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S3_IN0	R/W	Xh	STATE3 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S2_IN0	R/W	Xh	STATE2 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.100 SM_CFG4 Register (Offset = 393h) [Reset = XXh]

SM_CFG4 is shown in Table 7-363.

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Table 7-363 SM_CFG4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S3_IN1	R/W	Xh	STATE3 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S2_IN1	R/W	Xh	STATE2 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.101 SM_CFG5 Register (Offset = 394h) [Reset = XXh]

SM_CFG5 is shown in Table 7-364.

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Table 7-364 SM_CFG5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S3_IN2	R/W	Xh	STATE3 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S2_IN2	R/W	Xh	STATE2 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.102 SM_CFG6 Register (Offset = 395h) [Reset = XXh]

SM_CFG6 is shown in Table 7-365.

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Table 7-365 SM_CFG6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S5_IN0	R/W	Xh	STATE5 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S4_IN0	R/W	Xh	STATE4 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.103 SM_CFG7 Register (Offset = 396h) [Reset = XXh]

SM_CFG7 is shown in Table 7-366.

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Table 7-366 SM_CFG7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S5_IN1	R/W	Xh	STATE5 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S4_IN1	R/W	Xh	STATE4 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.104 SM_CFG8 Register (Offset = 397h) [Reset = XXh]

SM_CFG8 is shown in Table 7-367.

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Table 7-367 SM_CFG8 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S5_IN2	R/W	Xh	STATE5 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S4_IN2	R/W	Xh	STATE4 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.105 SM_CFG9 Register (Offset = 398h) [Reset = XXh]

SM_CFG9 is shown in Table 7-368.

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Table 7-368 SM_CFG9 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S7_IN0	R/W	Xh	STATE7 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S6_IN0	R/W	Xh	STATE6 IN0 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.106 SM_CFG10 Register (Offset = 399h) [Reset = XXh]

SM_CFG10 is shown in Table 7-369.

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Table 7-369 SM_CFG10 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6:4	SM_S7_IN1	R/W	Xh	STATE7 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S6_IN1	R/W	Xh	STATE6 IN1 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.107 SM_CFG11 Register (Offset = 39Ah) [Reset = 0Xh]

SM_CFG11 is shown in Table 7-370.

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Table 7-370 SM_CFG11 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SM_SYNC_EN	R/W	0h	State machine synchronous mode clock sync enable 0h = Disabled 1h = Enabled
6:4	SM_S7_IN2	R/W	0h	STATE7 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7
3	RESERVED	R	0h	Reserved
2:0	SM_S6_IN2	R/W	Xh	STATE6 IN2 transition FROM select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.108 SM_CFG12 Register (Offset = 3A7h) [Reset = X0h]

SM_CFG12 is shown in Table 7-371.

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Table 7-371 SM_CFG12 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	SM_CLK_SEL	R/W	0h	State machine CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3	SM_MODE	R/W	Xh	State machine synchronous mode select 0h = Asynchronous 1h = Synchronous
2:0	SM_INIT_STATE	R/W	Xh	State machine initial state select 0h = S0 1h = S1 2h = S2 3h = S3 4h = S4 5h = S5 6h = S6 7h = S7

4.4.3.109 SM_CFG13 Register (Offset = 3A8h) [Reset = X0h]

SM_CFG13 is shown in Table 7-372.

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Table 7-372 SM_CFG13 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S0_OUT_CFG	R/W	Xh

4.4.3.110 SM_CFG14 Register (Offset = 3A9h) [Reset = X0h]

SM_CFG14 is shown in Table 7-373.

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Table 7-373 SM_CFG14 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S1_OUT_CFG	R/W	Xh

4.4.3.111 SM_CFG15 Register (Offset = 3AAh) [Reset = X0h]

SM_CFG15 is shown in Table 7-374.

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Table 7-374 SM_CFG15 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S2_OUT_CFG	R/W	Xh

4.4.3.112 SM_CFG16 Register (Offset = 3ABh) [Reset = X0h]

SM_CFG16 is shown in Table 7-375.

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Table 7-375 SM_CFG16 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S3_OUT_CFG	R/W	Xh

4.4.3.113 SM_CFG17 Register (Offset = 3ACh) [Reset = X0h]

SM_CFG17 is shown in Table 7-376.

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Table 7-376 SM_CFG17 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S4_OUT_CFG	R/W	Xh

4.4.3.114 SM_CFG18 Register (Offset = 3ADh) [Reset = X0h]

SM_CFG18 is shown in Table 7-377.

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Table 7-377 SM_CFG18 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S5_OUT_CFG	R/W	Xh

4.4.3.115 SM_CFG19 Register (Offset = 3AEh) [Reset = X0h]

SM_CFG19 is shown in Table 7-378.

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Table 7-378 SM_CFG19 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S6_OUT_CFG	R/W	Xh

4.4.3.116 SM_CFG20 Register (Offset = 3AFh) [Reset = X0h]

SM_CFG20 is shown in Table 7-379.

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Table 7-379 SM_CFG20 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	S7_OUT_CFG	R/W	Xh

4.4.3.117 WDT_CFG0 Register (Offset = 3B8h) [Reset = X0h]

WDT_CFG0 is shown in Table 7-380.

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Table 7-380 WDT_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	WDT_TIMEOUT_DATA	R/W	Xh	WDT Timeout Period Counter DATA

4.4.3.118 WDT_CFG1 Register (Offset = 3B9h) [Reset = X0h]

WDT_CFG1 is shown in Table 7-381.

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Table 7-381 WDT_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	WDT_OUT_DATA	R/W	Xh	WDT Output Period Counter DATA

4.4.3.119 WDT_CFG2 Register (Offset = 3BAh) [Reset = 0Xh]

WDT_CFG2 is shown in Table 7-382.

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Table 7-382 WDT_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	WDT_CLK_SEL	R/W	0h	WDT CLK SEL 0h = OSC2 (25MHz) 1h = OSC2 / 4 2h = OSC1 (2MHz) 3h = OSC1 / 8 4h = OSC1 / 64 5h = OSC1 / 512 6h = OSC0 (2kHz) 7h = OSC0 / 8 8h = OSC0 / 64 9h = OSC0 / 512 Ah = OSC0 / 4096 Bh = OSC0 / 32768 Ch = OSC0 / 262144 Dh = Reserved Eh = Reserved Fh = External CLK from CMX
3:2	RESERVED	R	0h	Reserved
1	WDT_100X_EN	R/W	Xh	WDT 100X CLK multiplier EN 0h = Disabled 1h = Enabled
0	WDT_EN_SEL	R/W	Xh	WDT EN function select 0h = Reset CNT 1h = Pause CNT

4.4.3.120 PFLT0_CFG Register (Offset = 3BBh) [Reset = XXh]

PFLT0_CFG is shown in Table 7-383.

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Table 7-383 PFLT0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:4	PFLT_DLY_SEL	R/W	Xh	Programmable filter delay value select 0h = 125 ns 1h = 250 ns 2h = 375 ns 3h = 500 ns
3	PFLT_POL	R/W	Xh	Programmable filter output polarity select 0h = Non-inverted 1h = Inverted
2	RESERVED	R	0h	Reserved
1:0	PFLT_EDGE_SEL	R/W	Xh	Programmable filter edge select 0h = Both edge 1h = Rising edge 2h = Falling edge 3h = Filter

4.4.3.121 PFLT1_CFG Register (Offset = 3BCh) [Reset = XXh]

PFLT1_CFG is shown in Table 7-384.

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Table 7-384 PFLT1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:4	PFLT_DLY_SEL	R/W	Xh	Programmable filter delay value select 0h = 125 ns 1h = 250 ns 2h = 375 ns 3h = 500 ns
3	PFLT_POL	R/W	Xh	Programmable filter output polarity select 0h = Non-inverted 1h = Inverted
2	RESERVED	R	0h	Reserved
1:0	PFLT_EDGE_SEL	R/W	Xh	Programmable filter edge select 0h = Both edge 1h = Rising edge 2h = Falling edge 3h = Filter

4.4.3.122 FILT_CFG Register (Offset = 3BDh) [Reset = 0Xh]

FILT_CFG is shown in Table 7-385.

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Table 7-385 FILT_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	FLT_POL	R/W	Xh	Filter output polarity select 0h = Non-inverted 1h = Inverted
2	OTP_SPARE	R	0h	SPARE
1:0	FLT_EDGE_SEL	R/W	Xh	Filter / Edge detect edge select 0h = Both edge 1h = Rising edge 2h = Falling edge 3h = Filter

4.4.3.123 OSC0_CFG0 Register (Offset = 3BEh) [Reset = XXh]

OSC0_CFG0 is shown in Table 7-386.

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Table 7-386 OSC0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	CTRL_SRC	R/W	Xh	OSC power control source select 0h = From register 1h = From CMX
5	CTRL_SEL	R/W	Xh	OSC power control polarity select 0h = Power down (Low enables OSC, High disables OSC) 1h = Reserved
4	SRC_SEL	R/W	Xh	OSC frequency source select 0h = Internal OSC 1h = External clock
3:2	PDIV	R/W	Xh	OSC pre-divider select 0h = / 1 1h = / 2 2h = / 4 3h = / 8
1	RESERVED	R	0h	Reserved
0	PWR_MODE	R/W	Xh	OSC power mode select 0h = Auto power on 1h = Force power on

4.4.3.124 OSC0_CFG1 Register (Offset = 3BFh) [Reset = X0h]

OSC0_CFG1 is shown in Table 7-387.

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Table 7-387 OSC0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OUT1_EN	R/W	0h	OSC OUT1 enable 0h = Disabled 1h = Enabled
6:4	OUT1_DIV	R/W	0h	OSC OUT1 secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64
3	OUT0_EN	R/W	Xh	OSC OUT0 enable 0h = Disabled 1h = Enabled
2:0	OUT0_DIV	R/W	Xh	OSC OUT0 secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64

4.4.3.125 OSC1_CFG0 Register (Offset = 3C0h) [Reset = XXh]

OSC1_CFG0 is shown in Table 7-388.

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Table 7-388 OSC1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	CTRL_SRC	R/W	Xh	OSC power control source select 0h = From register 1h = From CMX
5	CTRL_SEL	R/W	Xh	OSC power control polarity select 0h = Power down (Low enables OSC, High disables OSC) 1h = Reserved
4	SRC_SEL	R/W	Xh	OSC frequency source select 0h = Internal OSC 1h = External clock
3:2	PDIV	R/W	Xh	OSC pre-divider select 0h = / 1 1h = / 2 2h = / 4 3h = / 8
1	RESERVED	R	0h	Reserved
0	PWR_MODE	R/W	Xh	OSC power mode select 0h = Auto power on 1h = Force power on

4.4.3.126 OSC1_CFG1 Register (Offset = 3C1h) [Reset = X0h]

OSC1_CFG1 is shown in Table 7-389.

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Table 7-389 OSC1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	OUT1_EN	R/W	0h	OSC OUT1 enable 0h = Disabled 1h = Enabled
6:4	OUT1_DIV	R/W	0h	OSC OUT1 secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64
3	OUT0_EN	R/W	Xh	OSC OUT0 enable 0h = Disabled 1h = Enabled
2:0	OUT0_DIV	R/W	Xh	OSC OUT0 secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64

4.4.3.127 OSC2_CFG0 Register (Offset = 3C2h) [Reset = 0Xh]

OSC2_CFG0 is shown in Table 7-390.

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Table 7-390 OSC2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	SU_DLY	R/W	0h	OSC startup delay control 0h = Enabled 1h = Disabled
6	CTRL_SRC	R/W	0h	OSC power control source select 0h = From register 1h = From CMX
5	CTRL_SEL	R/W	0h	OSC power control polarity select 0h = Power down (Low enables OSC, High disables OSC) 1h = Reserved
4	SRC_SEL	R/W	0h	OSC frequency source select 0h = Internal OSC 1h = External clock
3:2	PDIV	R/W	0h	OSC pre-divider select 0h = / 1 1h = / 2 2h = / 4 3h = / 8
1	RESERVED	R	0h	Reserved
0	PWR_MODE	R/W	Xh	OSC power mode select 0h = Auto power on 1h = Force power on

4.4.3.128 OSC2_CFG1 Register (Offset = 3C3h) [Reset = 0Xh]

OSC2_CFG1 is shown in Table 7-391.

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Table 7-391 OSC2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	RESERVED	R	0h	Reserved
3	OUT_EN	R/W	Xh	OSC OUT enable 0h = Disabled 1h = Enabled
2:0	OUT_DIV	R/W	Xh	OSC OUT secondary divider select 0h = / 1 1h = / 2 2h = / 3 3h = / 4 4h = / 8 5h = / 12 6h = / 24 7h = / 64

4.4.3.129 ACMP0_CFG0 Register (Offset = 3C6h) [Reset = X0h]

ACMP0_CFG0 is shown in Table 7-392.

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Table 7-392 ACMP0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	BW_SEL	R/W	0h	ACMP bandwidth select 0h = High bandwidth 1h = Low bandwidth 2h = Reserved 3h = Reserved
5:4	INP_SEL	R/W	0h	ACMP input source select 0h = ACMP IN0 1h = ACMP IN1 2h = ACMP IN2 3h = ACMP IN3
3:2	GAIN_SEL	R/W	Xh	ACMP gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	ACMP hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.130 ACMP0_CFG1 Register (Offset = 3C7h) [Reset = XXh]

ACMP0_CFG1 is shown in Table 7-393.

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Table 7-393 ACMP0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	ACMP VREF select 0h = 32 mV 1h = 64 mV 2h = 96 mV 3h = 128 mV 4h = 160 mV 5h = 192 mV 6h = 224 mV 7h = 256 mV 8h = 288 mV 9h = 320 mV Ah = 352 mV Bh = 384 mV Ch = 416 mV Dh = 448 mV Eh = 480 mV Fh = 512 mV 10h = 544 mV 11h = 576 mV 12h = 608 mV 13h = 640 mV 14h = 672 mV 15h = 704 mV 16h = 736 mV 17h = 768 mV 18h = 800 mV 19h = 832 mV 1Ah = 864 mV 1Bh = 896 mV 1Ch = 928 mV 1Dh = 960 mV 1Eh = 992 mV 1Fh = 1.024 V 20h = 1.056 V 21h = 1.088 V 22h = 1.120 V 23h = 1.152 V 24h = 1.184 V 25h = 1.216 V 26h = 1.248 V 27h = 1.280 V 28h = 1.312 V 29h = 1.344 V 2Ah = 1.376 V 2Bh = 1.408 V 2Ch = 1.440 V 2Dh = 1.472 V 2Eh = 1.504 V 2Fh = 1.536 V 30h = 1.568 V 31h = 1.600 V 32h = 1.632 V 33h = 1.664 V 34h = 1.696 V 35h = 1.728 V 36h = 1.760 V 37h = 1.792 V 38h = 1.824 V 39h = 1.856 V 3Ah = 1.888 V 3Bh = 1.920 V 3Ch = 1.952 V 3Dh = 1.984 V 3Eh = 2.016 V 3Fh = External VREF

4.4.3.131 ACMP1_CFG0 Register (Offset = 3C8h) [Reset = X0h]

ACMP1_CFG0 is shown in Table 7-394.

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Table 7-394 ACMP1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	BW_SEL	R/W	0h	ACMP bandwidth select 0h = High bandwidth 1h = Low bandwidth 2h = Reserved 3h = Reserved
5:4	INP_SEL	R/W	0h	ACMP input source select 0h = ACMP IN0 1h = ACMP IN1 2h = ACMP IN2 3h = ACMP IN3
3:2	GAIN_SEL	R/W	Xh	ACMP gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	ACMP hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.132 ACMP1_CFG1 Register (Offset = 3C9h) [Reset = XXh]

ACMP1_CFG1 is shown in Table 7-395.

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Table 7-395 ACMP1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	ACMP VREF select 0h = 32 mV 1h = 64 mV 2h = 96 mV 3h = 128 mV 4h = 160 mV 5h = 192 mV 6h = 224 mV 7h = 256 mV 8h = 288 mV 9h = 320 mV Ah = 352 mV Bh = 384 mV Ch = 416 mV Dh = 448 mV Eh = 480 mV Fh = 512 mV 10h = 544 mV 11h = 576 mV 12h = 608 mV 13h = 640 mV 14h = 672 mV 15h = 704 mV 16h = 736 mV 17h = 768 mV 18h = 800 mV 19h = 832 mV 1Ah = 864 mV 1Bh = 896 mV 1Ch = 928 mV 1Dh = 960 mV 1Eh = 992 mV 1Fh = 1.024 V 20h = 1.056 V 21h = 1.088 V 22h = 1.120 V 23h = 1.152 V 24h = 1.184 V 25h = 1.216 V 26h = 1.248 V 27h = 1.280 V 28h = 1.312 V 29h = 1.344 V 2Ah = 1.376 V 2Bh = 1.408 V 2Ch = 1.440 V 2Dh = 1.472 V 2Eh = 1.504 V 2Fh = 1.536 V 30h = 1.568 V 31h = 1.600 V 32h = 1.632 V 33h = 1.664 V 34h = 1.696 V 35h = 1.728 V 36h = 1.760 V 37h = 1.792 V 38h = 1.824 V 39h = 1.856 V 3Ah = 1.888 V 3Bh = 1.920 V 3Ch = 1.952 V 3Dh = 1.984 V 3Eh = 2.016 V 3Fh = External VREF

4.4.3.133 ACMP2_CFG0 Register (Offset = 3CAh) [Reset = X0h]

ACMP2_CFG0 is shown in Table 7-396.

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Table 7-396 ACMP2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	BW_SEL	R/W	0h	ACMP bandwidth select 0h = High bandwidth 1h = Low bandwidth 2h = Reserved 3h = Reserved
5:4	INP_SEL	R/W	0h	ACMP input source select 0h = ACMP IN0 1h = ACMP IN1 2h = ACMP IN2 3h = ACMP IN3
3:2	GAIN_SEL	R/W	Xh	ACMP gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	ACMP hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.134 ACMP2_CFG1 Register (Offset = 3CBh) [Reset = XXh]

ACMP2_CFG1 is shown in Table 7-397.

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Table 7-397 ACMP2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	ACMP VREF select 0h = 32 mV 1h = 64 mV 2h = 96 mV 3h = 128 mV 4h = 160 mV 5h = 192 mV 6h = 224 mV 7h = 256 mV 8h = 288 mV 9h = 320 mV Ah = 352 mV Bh = 384 mV Ch = 416 mV Dh = 448 mV Eh = 480 mV Fh = 512 mV 10h = 544 mV 11h = 576 mV 12h = 608 mV 13h = 640 mV 14h = 672 mV 15h = 704 mV 16h = 736 mV 17h = 768 mV 18h = 800 mV 19h = 832 mV 1Ah = 864 mV 1Bh = 896 mV 1Ch = 928 mV 1Dh = 960 mV 1Eh = 992 mV 1Fh = 1.024 V 20h = 1.056 V 21h = 1.088 V 22h = 1.120 V 23h = 1.152 V 24h = 1.184 V 25h = 1.216 V 26h = 1.248 V 27h = 1.280 V 28h = 1.312 V 29h = 1.344 V 2Ah = 1.376 V 2Bh = 1.408 V 2Ch = 1.440 V 2Dh = 1.472 V 2Eh = 1.504 V 2Fh = 1.536 V 30h = 1.568 V 31h = 1.600 V 32h = 1.632 V 33h = 1.664 V 34h = 1.696 V 35h = 1.728 V 36h = 1.760 V 37h = 1.792 V 38h = 1.824 V 39h = 1.856 V 3Ah = 1.888 V 3Bh = 1.920 V 3Ch = 1.952 V 3Dh = 1.984 V 3Eh = 2.016 V 3Fh = External VREF

4.4.3.135 ACMP3_CFG0 Register (Offset = 3CCh) [Reset = X0h]

ACMP3_CFG0 is shown in Table 7-398.

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Table 7-398 ACMP3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	BW_SEL	R/W	0h	ACMP bandwidth select 0h = High bandwidth 1h = Low bandwidth 2h = Reserved 3h = Reserved
5:4	INP_SEL	R/W	0h	ACMP input source select 0h = ACMP IN0 1h = ACMP IN1 2h = ACMP IN2 3h = ACMP IN3
3:2	GAIN_SEL	R/W	Xh	ACMP gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	ACMP hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.136 ACMP3_CFG1 Register (Offset = 3CDh) [Reset = XXh]

ACMP3_CFG1 is shown in Table 7-399.

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Table 7-399 ACMP3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL	R/W	Xh	ACMP VREF select 0h = 32 mV 1h = 64 mV 2h = 96 mV 3h = 128 mV 4h = 160 mV 5h = 192 mV 6h = 224 mV 7h = 256 mV 8h = 288 mV 9h = 320 mV Ah = 352 mV Bh = 384 mV Ch = 416 mV Dh = 448 mV Eh = 480 mV Fh = 512 mV 10h = 544 mV 11h = 576 mV 12h = 608 mV 13h = 640 mV 14h = 672 mV 15h = 704 mV 16h = 736 mV 17h = 768 mV 18h = 800 mV 19h = 832 mV 1Ah = 864 mV 1Bh = 896 mV 1Ch = 928 mV 1Dh = 960 mV 1Eh = 992 mV 1Fh = 1.024 V 20h = 1.056 V 21h = 1.088 V 22h = 1.120 V 23h = 1.152 V 24h = 1.184 V 25h = 1.216 V 26h = 1.248 V 27h = 1.280 V 28h = 1.312 V 29h = 1.344 V 2Ah = 1.376 V 2Bh = 1.408 V 2Ch = 1.440 V 2Dh = 1.472 V 2Eh = 1.504 V 2Fh = 1.536 V 30h = 1.568 V 31h = 1.600 V 32h = 1.632 V 33h = 1.664 V 34h = 1.696 V 35h = 1.728 V 36h = 1.760 V 37h = 1.792 V 38h = 1.824 V 39h = 1.856 V 3Ah = 1.888 V 3Bh = 1.920 V 3Ch = 1.952 V 3Dh = 1.984 V 3Eh = 2.016 V 3Fh = External VREF

4.4.3.137 MCACMP_CFG0 Register (Offset = 3CFh) [Reset = 0Xh]

MCACMP_CFG0 is shown in Table 7-400.

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Table 7-400 MCACMP_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	TS_INP_EN	R/W	0h	Temperature sensor input to McACMP enable 0h = Disabled 1h = Enabled
6	VCC_INP_EN	R/W	0h	VCC input to McACMP enable 0h = Disabled 1h = Enabled
5	SYNC_EN	R/W	0h	McACMP output synchronicity select 0h = Asychronous 1h = Synchronous
4	MCS_MODE	R/W	0h	McACMP trigger mode select 0h = Level sensitive EN mode 1h = Edge sensitive EN mode
3:2	CH_EN	R/W	0h	Number of channels sampled select 0h = 1 channel 1h = 2 channels 2h = 3 channels 3h = 4 channels
1	RESERVED	R	0h	Reserved
0	MCS_EN	R/W	Xh	Sampling mode select 0h = Regular mode (single channel) 1h = Multi-channel mode

4.4.3.138 MCACMP_CFG1 Register (Offset = 3D0h) [Reset = 0Xh]

MCACMP_CFG1 is shown in Table 7-401.

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Table 7-401 MCACMP_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	BW_SEL	R/W	0h	McACMP bandwidth select 0h = High bandwidth 1h = Low bandwidth 2h = Reserved 3h = Reserved
5:3	RESERVED	R	0h	Reserved
2	EDGE_SEL	R/W	Xh	McACMP sampling edge select 0h = Sample on negative edge of CLK 1h = Sample on positive edge of CLK
1:0	MCS_CLK_SEL	R/W	Xh	McACMP CLK select 0h = OSC1 (2MHz) / 20 1h = OSC1 / 40 2h = OSC0 (2kHz) 3h = OSC0 / 2

4.4.3.139 MCACMP_CH0_CFG0 Register (Offset = 3D1h) [Reset = XXh]

MCACMP_CH0_CFG0 is shown in Table 7-402.

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Table 7-402 MCACMP_CH0_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH0 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH0 input source select 0h = McACMP IN0 1h = McACMP IN1 2h = McACMP IN2 (or VCC) 3h = McACMP IN3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH0 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH0 hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.140 MCACMP_CH0_CFG1 Register (Offset = 3D2h) [Reset = X0h]

MCACMP_CH0_CFG1 is shown in Table 7-403.

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Table 7-403 MCACMP_CH0_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	CH_VREF_SEL	R/W	0h	No. of VREF select 0h = 1 VREF 1h = 2 VREF 2h = Reserved 3h = Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH0_0 VREF select 0h = 32 mV 1h = 64 mV 2h = 96 mV 3h = 128 mV 4h = 160 mV 5h = 192 mV 6h = 224 mV 7h = 256 mV 8h = 288 mV 9h = 320 mV Ah = 352 mV Bh = 384 mV Ch = 416 mV Dh = 448 mV Eh = 480 mV Fh = 512 mV 10h = 544 mV 11h = 576 mV 12h = 608 mV 13h = 640 mV 14h = 672 mV 15h = 704 mV 16h = 736 mV 17h = 768 mV 18h = 800 mV 19h = 832 mV 1Ah = 864 mV 1Bh = 896 mV 1Ch = 928 mV 1Dh = 960 mV 1Eh = 992 mV 1Fh = 1.024 V 20h = 1.056 V 21h = 1.088 V 22h = 1.120 V 23h = 1.152 V 24h = 1.184 V 25h = 1.216 V 26h = 1.248 V 27h = 1.280 V 28h = 1.312 V 29h = 1.344 V 2Ah = 1.376 V 2Bh = 1.408 V 2Ch = 1.440 V 2Dh = 1.472 V 2Eh = 1.504 V 2Fh = 1.536 V 30h = 1.568 V 31h = 1.600 V 32h = 1.632 V 33h = 1.664 V 34h = 1.696 V 35h = 1.728 V 36h = 1.760 V 37h = 1.792 V 38h = 1.824 V 39h = 1.856 V 3Ah = 1.888 V 3Bh = 1.920 V 3Ch = 1.952 V 3Dh = 1.984 V 3Eh = 2.016 V 3Fh = External VREF

4.4.3.141 MCACMP_CH0_CFG2 Register (Offset = 3D3h) [Reset = XXh]

MCACMP_CH0_CFG2 is shown in Table 7-404.

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Table 7-404 MCACMP_CH0_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL1	R/W	Xh	McACMP CH0_1 VREF select (same options as CH0_0)

4.4.3.142 MCACMP_CH1_CFG0 Register (Offset = 3D6h) [Reset = XXh]

MCACMP_CH1_CFG0 is shown in Table 7-405.

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Table 7-405 MCACMP_CH1_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH1 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH1 input source select 0h = McACMP IN0 1h = McACMP IN1 2h = McACMP IN2 (or VCC) 3h = McACMP IN3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH1 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH1 hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.143 MCACMP_CH1_CFG1 Register (Offset = 3D7h) [Reset = X0h]

MCACMP_CH1_CFG1 is shown in Table 7-406.

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Table 7-406 MCACMP_CH1_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	CH_VREF_SEL	R/W	0h	No. of VREF select 0h = 1 VREF 1h = 2 VREF 2h = Reserved 3h = Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH1_0 VREF select (same options as CH0_0)

4.4.3.144 MCACMP_CH1_CFG2 Register (Offset = 3D8h) [Reset = XXh]

MCACMP_CH1_CFG2 is shown in Table 7-407.

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Table 7-407 MCACMP_CH1_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL1	R/W	Xh	McACMP CH1_1 VREF select (same options as CH0_0)

4.4.3.145 MCACMP_CH2_CFG0 Register (Offset = 3DBh) [Reset = XXh]

MCACMP_CH2_CFG0 is shown in Table 7-408.

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Table 7-408 MCACMP_CH2_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH2 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH2 input source select 0h = McACMP IN0 1h = McACMP IN1 2h = McACMP IN2 (or VCC) 3h = McACMP IN3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH2 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH2 hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.146 MCACMP_CH2_CFG1 Register (Offset = 3DCh) [Reset = X0h]

MCACMP_CH2_CFG1 is shown in Table 7-409.

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Table 7-409 MCACMP_CH2_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	CH_VREF_SEL	R/W	0h	No. of VREF select 0h = 1 VREF 1h = 2 VREF 2h = Reserved 3h = Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH2_0 VREF select (same options as CH0_0)

4.4.3.147 MCACMP_CH2_CFG2 Register (Offset = 3DDh) [Reset = XXh]

MCACMP_CH2_CFG2 is shown in Table 7-410.

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Table 7-410 MCACMP_CH2_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL1	R/W	Xh	McACMP CH2_1 VREF select (same options as CH0_0)

4.4.3.148 MCACMP_CH3_CFG0 Register (Offset = 3E0h) [Reset = XXh]

MCACMP_CH3_CFG0 is shown in Table 7-411.

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Table 7-411 MCACMP_CH3_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	RESERVED	R	0h	Reserved
6	RST_EN	R/W	Xh	McACMP CH3 RST EN select 0h = Disabled 1h = Enabled
5:4	INP_SEL	R/W	Xh	McACMP CH3 input source seelct 0h = McACMP IN0 1h = McACMP IN1 2h = McACMP IN2 (or VCC) 3h = McACMP IN3 (or TS)
3:2	GAIN_SEL	R/W	Xh	McACMP CH3 gain select 0h = 1X 1h = 0.5X 2h = 0.33X 3h = 0.25X
1:0	HYS_SEL	R/W	Xh	McACMP CH3 hysteresis select 0h = 0 mV 1h = 64 mV 2h = 128 mV 3h = 192 mV

4.4.3.149 MCACMP_CH3_CFG1 Register (Offset = 3E1h) [Reset = X0h]

MCACMP_CH3_CFG1 is shown in Table 7-412.

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Table 7-412 MCACMP_CH3_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	CH_VREF_SEL	R/W	0h	No. of VREF select 0h = 1 VREF 1h = 2 VREF 2h = Reserved 3h = Reserved
5:0	VREF_SEL	R/W	Xh	McACMP CH3_0 VREF select (same options as CH0_0)

4.4.3.150 MCACMP_CH3_CFG2 Register (Offset = 3E2h) [Reset = XXh]

MCACMP_CH3_CFG2 is shown in Table 7-413.

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Table 7-413 MCACMP_CH3_CFG2 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:6	RESERVED	R	0h	Reserved
5:0	VREF_SEL1	R/W	Xh	McACMP CH3_1 VREF select (same options as CH0_0)

4.4.3.151 AMUX0_CFG Register (Offset = 3E5h) [Reset = 0Xh]

AMUX0_CFG is shown in Table 7-414.

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Table 7-414 AMUX0_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0h	Reserved
0	AMUX_EN	R/W	Xh	AMUX EN 0h = Disabled 1h = Enabled

4.4.3.152 AMUX1_CFG Register (Offset = 3E6h) [Reset = 0Xh]

AMUX1_CFG is shown in Table 7-415.

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Table 7-415 AMUX1_CFG Register Field Descriptions

Bit	Field	Type	Reset	Description
7:1	RESERVED	R	0h	Reserved
0	AMUX_EN	R/W	Xh	AMUX EN 0h = Disabled 1h = Enabled

4.4.3.153 SER_COMM_CFG0 Register (Offset = 3F2h) [Reset = X0h]

SER_COMM_CFG0 is shown in Table 7-416.

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Table 7-416 SER_COMM_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	I2C_ADDR_SRC_SEL	R/W	0h	I2C HW address source select (bitwise) 0h = OTP 1h = IO
3	I2C_IO_LAT	R/W	Xh	I2C HW addressing IO latching select 0h = Enabled 1h = Disabled
2	I2C_RST_EN	R/W	Xh	I2C Global Reset listening select 0h = Disabled 1h = Enabled
1	I2C_EN	R/W	Xh	I2C serial communications enable select 0h = Disabled 1h = Enabled
0	SPI_EN	R/W	Xh	SPI serial communications enable select 0h = Disabled 1h = Enabled

4.4.3.154 SER_COMM_CFG1 Register (Offset = 3F3h) [Reset = 00h]

SER_COMM_CFG1 is shown in Table 7-417.

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Table 7-417 SER_COMM_CFG1 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:4	I2C_ADDR_MSB	R/W	0h	I2C HW address
3:1	I2C_ADDR_LSB	R/W	0h	I2C HW address
0	RESERVED	R	0h	Reserved

4.4.3.155 MISC_CFG0 Register (Offset = 3F7h) [Reset = 00h]

MISC_CFG0 is shown in Table 7-418.

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Table 7-418 MISC_CFG0 Register Field Descriptions

Bit	Field	Type	Reset	Description
7	GPIO_QC	R/W	0h	GPIO quick charge control 0h = Disabled 1h = Enabled
6	CFG_RD_LCK	R/W	0h	CFG read lock control 0h = Disabled 1h = Enabled
5	CFG_WR_LCK	R/W	0h	CFG write lock control 0h = Disabled 1h = Enabled
4	OTP_WR_LCK	R/W	0h	OTP write lock control 0h = Disabled 1h = Enabled
3:2	USER_LCK	R/W	0h	USER read/write lock control 0h = R/W to all non-reserved, non-read-only registers 1h = R/W to only Counter DATA, Watchdog Timer DATA, and Pattern Generator registers 2h = R/W to only State Machine registers 3h = R/W to only Voltage Reference select registers
1:0	RESERVED	R	0h	Reserved

4.4.3.156 DEVICE_ID4 Register (Offset = 3FAh) [Reset = X0h]

DEVICE_ID4 is shown in Table 7-419.

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Table 7-419 DEVICE_ID4 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID4	R	Xh	Device ID

4.4.3.157 DEVICE_ID5 Register (Offset = 3FBh) [Reset = X0h]

DEVICE_ID5 is shown in Table 7-420.

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Table 7-420 DEVICE_ID5 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID5	R	Xh	Device ID

4.4.3.158 DEVICE_ID6 Register (Offset = 3FCh) [Reset = X0h]

DEVICE_ID6 is shown in Table 7-421.

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Table 7-421 DEVICE_ID6 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID6	R	Xh	Device ID

4.4.3.159 DEVICE_ID7 Register (Offset = 3FDh) [Reset = X0h]

DEVICE_ID7 is shown in Table 7-422.

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Table 7-422 DEVICE_ID7 Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	DEVICE_ID7	R	Xh	Device ID

4.4.3.160 CRC_LSB Register (Offset = 3FEh) [Reset = X0h]

CRC_LSB is shown in Table 7-423.

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Table 7-423 CRC_LSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CRC_LSB	R/W	Xh	CRC LSB for 2kb OTP

4.4.3.161 CRC_MSB Register (Offset = 3FFh) [Reset = X0h]

CRC_MSB is shown in Table 7-424.

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Table 7-424 CRC_MSB Register Field Descriptions

Bit	Field	Type	Reset	Description
7:0	CRC_MSB	R/W	Xh	CRC MSB for 2kb OTP