SCPS286 July   2025 TPLD2001

ADVANCE INFORMATION  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Supply Current Characteristics
    7. 5.7 Switching Characteristics
    8. 5.8 I2C Bus Timing Requirements
    9. 5.9 SPI Timing Requirements
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  I/O Pins
        1. 7.3.1.1 Input Modes
        2. 7.3.1.2 Output Modes
        3. 7.3.1.3 Pull-Up or Pull-Down Resistors
      2. 7.3.2  Connection Mux
      3. 7.3.3  Configurable Use Logic Blocks
        1. 7.3.3.1 2-Bit LUT or D Flip-Flop/Latch macro-cell
          1. 7.3.3.1.1 2-Bit LUT
          2. 7.3.3.1.2 D Flip-Flop/Latch
        2. 7.3.3.2 2-Bit LUT or Pattern Generator macro-cell
          1. 7.3.3.2.1 2-Bit LUT
          2. 7.3.3.2.2 Pattern Generator
        3. 7.3.3.3 3-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.3.1 3-Bit LUT
          2. 7.3.3.3.2 D Flip-Flop/Latch with Reset/Set
        4. 7.3.3.4 3-Bit LUT or D Flip-Flop/Latch or Shift Register macro-cell
          1. 7.3.3.4.1 3-Bit LUT
          2. 7.3.3.4.2 D Flip-Flop/Latch with Reset/Set
          3. 7.3.3.4.3 8-Bit Shift Register
        5. 7.3.3.5 4-Bit LUT or D Flip-Flop/Latch with Reset/Set macro-cell
          1. 7.3.3.5.1 4-Bit LUT
          2. 7.3.3.5.2 D Flip-Flop/Latch with Reset/Set
      4. 7.3.4  Configurable Logic and Timing blocks
        1. 7.3.4.1 3-Bit LUT
        2. 7.3.4.2 D Flip-Flop/Latch with Reset/Set
        3. 7.3.4.3 Counters/Delay Generators (CNT/DLY)
          1. 7.3.4.3.1 Delay Mode
          2. 7.3.4.3.2 Reset Counter Mode
          3. 7.3.4.3.3 One-Shot Mode
          4. 7.3.4.3.4 Frequency Comparator Mode
          5. 7.3.4.3.5 Edge Detector Mode
          6. 7.3.4.3.6 Delayed Edge Detector Mode
        4. 7.3.4.4 LUT/DFF + CNT modes
      5. 7.3.5  Programmable Deglitch Filter or Edge Detector
      6. 7.3.6  Deglitch Filter or Edge Detector
      7. 7.3.7  State Machine (SM)
        1. 7.3.7.1 State Machine Inputs
        2. 7.3.7.2 State Machine Outputs
        3. 7.3.7.3 Configuring the State Machine
        4. 7.3.7.4 State Machine Timing Considerations
      8. 7.3.8  8-Bit Counters/Delay Generators/Finite State Machines
      9. 7.3.9  PWM Generators
      10. 7.3.10 Watchdog Timer
      11. 7.3.11 Analog Comparators
        1. 7.3.11.1 Discrete Analog Comparator (ACMP)
        2. 7.3.11.2 Multi-channel Analog Comparator (McACMP)
      12. 7.3.12 Voltage Reference (VREF)
      13. 7.3.13 Analog Temperature Sensor (TS)
      14. 7.3.14 Analog Multiplexer (AMUX)
      15. 7.3.15 Oscillators
        1. 7.3.15.1 2kHz Fixed Frequency Oscillator
        2. 7.3.15.2 2MHz Fixed Frequency Oscillator
        3. 7.3.15.3 25MHz Fixed Frequency Oscillator
        4. 7.3.15.4 Oscillator Power Modes
      16. 7.3.16 Serial Communications
        1. 7.3.16.1 I2C Mode
        2. 7.3.16.2 SPI Mode
        3. 7.3.16.3 Virtual I/Os
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Power Supply Control Modes
      3. 7.4.3 Protection Features
        1. 7.4.3.1 Device Read/Write Lock
        2. 7.4.3.2 OTP Cyclic Redundancy Check (CRC)
      4. 7.4.4 Programming
        1. 7.4.4.1 Selectable I2C/SPI Interface
        2. 7.4.4.2 One-Time Programmable Memory (OTP)
        3. 7.4.4.3 Intel HEX File Format
        4. 7.4.4.4 TPLD2001 Registers
          1. 7.4.4.4.1 TPLD2001_User Registers
          2. 7.4.4.4.2 TPLD2001_Cfg_0 Registers
          3. 7.4.4.4.3 TPLD2001_Cfg_1 Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Tape and Reel Information
    2. 11.2 Mechanical Data

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Supply and Power-on Reset
VPORR Power-on reset voltage, VCC rising VI = VCC or GND, IO = 0 1.27 1.39 V
VPORF Power-on reset voltage, VCC falling VI = VCC or GND, IO = 0 1.14 1.26 V
tSU Startup time from VCC rising past VPORR to GPO becoming active 0.76 ms
VPP Programming voltage 7.5 8 V
Digital IO
VT+ Positive-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.94 1.27 V
3.3V ± 0.3V 1.55 2.17
5V ± 0.5V 2.21 3.19
VT- Negative-going input threshold voltage Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.58 0.94 V
3.3V ± 0.3V 1.1 1.79
5V ± 0.5V 1.63 2.7
VHYS Schmitt-Trigger hysteresis (VT+ - VT-) Logic Input with Schmitt Trigger 1.8V ± 0.09V 0.08 0.36 V
3.3V ± 0.3V 0.15 0.66
5V ± 0.5V 0.22 1.00
VOH High-level output voltage Push-pull 1X IOH = -100µA 1.8V ± 0.09V 1.68 V
Push-pull 2X 1.69
Push-pull 1X IOH = -3mA 3.3V ± 0.3V 2.47
Push-pull 2X 2.63
Push-pull 1X IOH = -5mA 5V ± 0.5V 3.84
Push-pull 2X 4.02
VOH High-level output voltage SPI SDO IOH = -2mA 1.71V to 5.5V (0.8 × VCC) V
VOL Low-level output voltage Push-pull 1X IOL = 100µA 1.8V ± 0.09V 0.01 V
Push-pull 2X 0.01
Open-drain NMOS 1X 0.01
Open-drain NMOS 2X 0.01
Push-pull 1X IOL = 3mA 3.3V ± 0.3V 0.1
Push-pull 2X 0.1
Open-drain NMOS 1X 0.1
Open-drain NMOS 2X 0.1
Push-pull 1X IOL = 5mA 5V ± 0.5V 0.12
Push-pull 2X 0.12
Open-drain NMOS 1X 0.12
Open-drain NMOS 2X 0.12
VOL Low-level output voltage I2C SCL, SDA pins (Open-drain NMOS 4X) IOL = 3mA VCC > 2V 0.4 V
I2C SCL, SDA pins (Open-drain NMOS 4X) IOL = 2mA VCC ≤ 2V (0.2 × VCC)
SPI SDO pin IOL = 2mA 1.71V to 5.5V (0.2 × VCC)
IOL Low-level output current I2C SCL, SDA pins (Standard mode, Fast mode) VOL = 0.4V
 1.71V to 5.5V 3 mA
I2C SCL, SDA pins (Fast mode Plus) 20
II Input leakage current All pins VI = VCC 1.71V to 5.5V ±1 µA
VI = GND ±1
IOZ Off-state (high-Z state) output current VO = 0 to 5.5V 1.71V to 5.5V ±1 µA
Ioff Input/output power-off leakage current VI or VO = 5.5V 0V ±5 µA
FOUT Max output frequency (1) All IOs
Push-pull 1X or Push-pull 2X		 CL = 15pF 1.8V ± 0.09V 8 MHz
3.3V ± 0.3V 8 MHz
5V ± 0.5V 8 MHz
FOUT Max output frequency (1) IO14, IO15, IO17 only
Push-pull 1X or Push-pull 2X		 CL = 15pF 1.8V ± 0.09V 10 MHz
3.3V ± 0.3V 12 MHz
5V ± 0.5V 12 MHz
Rpu(int) Internal pull-up resistance 1 MΩ
100 kΩ
10 kΩ
Rpd(int) Internal pull-down resistance 1 MΩ
100 kΩ
10 kΩ
CI Input pin capacitance each input pin VI = VCC or GND 1.71V to 5.5V 4 10 pF
CI Input pin capacitance I2C SCL pin
SPI SDI, SCK, nCS pins		 VI = VCC or GND 1.71V to 5.5V 4 10 pF
CIO Input-output pin capacitance each I/O pin VIO = VCC or GND 1.71V to 5.5V 4 10 pF
CIO Input-output pin capacitance I2C SDA pin VIO = VCC or GND 1.71V to 5.5V 4 10 pF
Analog Comparator - Discrete Analog Comparator
tstart Start time ACMP power on
delay		 Bandgap force on,
Oscillator force on		 1.71V to 5.5V 110 µs
Bandgap force on,
Oscillator auto on		 110
Bandgap auto on,
Oscillator force on		 110
Bandgap auto on,
Oscillator auto on
VAI Input voltage Positive input 1.71V to 5.5V 0 VCC V
Negative input 0 2.016
Voffset Input offset voltage TA = 25℃ VHYS = 0mV,
Gain = 1,
VREF = 32mV to 1504mV		 1.71V to 5.5V -12 12 mV
–40°C < TA ≤ 125°C -15 15
TA = 25℃ VHYS = 0mV,
Gain = 1,
VREF = 32mV to 2016mV		 2.3V to 5.5V -12 12
–40°C < TA ≤ 125°C -15 15
dVIO/dT Input offset voltage drift –40°C < TA ≤ 125°C VHYS = 0mV,
Gain = 1,
VREF = 32mV to 1504mV		 1.71V to 5.5V ±7 µV/ºC
VHYS = 0mV,
Gain = 1,
VREF = 32mV to 2016mV		 2.3V to 5.5V ±7
IB Input bias current 1 µA
CID Input capacitance, differential 3 pF
CIM Input capacitance, common mode 3 pF
PROP Propagation delay,
response time		 Low to High, 
Low bandwidth enabled		 Gain = 1,
Vref = 32mV to 1504mV,
Overdrive = 32mV		 1.71V to 5.5V 11 µs
High to Low, 
Low bandwidth enabled		 10
Low to High, 
Low bandwidth disabled		 2
High to Low, 
Low bandwidth disabled		 2
Low to High, 
Low bandwidth enabled		 Gain = 1,
Vref = 32mV to 2016mV,
Overdrive = 32mV		 2.3V to 5.5V 11
High to Low, 
Low bandwidth enabled		 8
Low to High, 
Low bandwidth disabled		 2
High to Low, 
Low bandwidth disabled		 2
Analog Comparator - Multi-channel Analog Comparator
tstart Start time ACMP power on
delay		 Bandgap force on
OSC force on
1-channel, 1-VREF		 1.71V to 5.5V 130 µs
Bandgap force on
OSC0 force on
Multi-channel mode		 2.9 ms
Bandgap force on
OSC1 force on
Multi-channel mode		 150 µs
VAI Input voltage Positive input 1.71V to 5.5V 0 VCC V
Negative input 0 2.016
Voffset Input offset voltage TA = 25℃ VHYS = 0mV,
Gain = 1,
VREF = 32mV to 1504mV		 1.71V to 5.5V -12 12 mV
–40°C < TA ≤ 125°C -15 15
TA = 25℃ VHYS = 0mV,
Gain = 1,
VREF = 32mV to 2016mV		 2.3V to 5.5V -12 12
–40°C < TA ≤ 125°C -15 15
dVIO/dT Input offset voltage drift –40°C < TA ≤ 125°C VHYS = 0mV,
Gain = 1,
VREF = 32mV to 1504mV		 1.71V to 5.5V ±7 µV/ºC
VHYS = 0mV,
Gain = 1,
VREF = 32mV to 2016mV		 2.3V to 5.5V ±7
IB Input bias current 1 µA
CID Input capacitance, differential 3 pF
CIM Input capacitance, common mode 3 pF
PROP Propagation delay,
response time		 Low to High, 
Low bandwidth enabled		 1 channel,
Gain = 1,
Vref = 32mV to 1504mV,
Overdrive = 32mV		 1.71V to 5.5V 11 µs
High to Low, 
Low bandwidth enabled		 10
Low to High, 
Low bandwidth disabled		 1 channel,
Gain = 1,
Vref = 32mV to 1504mV,
Overdrive = 32mV		 1.71V to 5.5V 2
High to Low, 
Low bandwidth disabled		 2
Low to High, 
Low bandwidth enabled		 1 channel,
Gain = 1,
Vref = 32mV to 2016mV,
Overdrive = 32mV		 2.3V to 5.5V 11 µs
High to Low, 
Low bandwidth enabled		 8 µs
Low to High, 
Low bandwidth disabled		 1 channel,
Gain = 1,
Vref = 32mV to 2016mV,
Overdrive = 32mV		 2.3V to 5.5V 2 µs
High to Low, 
Low bandwidth disabled		 2 µs
Low to High Multi-channel,
Gain = 1,
Vref = 32mV to 1504mV,
Overdrive = 32mV		 1.71V to 5.5V (tSMP_CLK × CH) µs
High to Low (tSMP_CLK × CH) µs
Low to High Multi-channel,
Gain = 1,
Vref = 32mV to 2016mV,
Overdrive = 32mV		 2.3V to 5.5V (tSMP_CLK × CH) µs
High to Low (tSMP_CLK × CH) µs
Analog Comparator - Hysteresis
VHYS Built-in hysteresis –40°C < TA ≤ 125°C VHYS = 64 mV 1.71V to 5.5V 54.4 66.9 71.0 mV
VHYS = 128 mV 109.0 130.8 135.0
VHYS = 192 mV 190.0 194.8 199.2
Analog Comparator - Input Gain
Rsin Series input resistance Gain = 0.5 1.71V to 5.5V 1 MΩ
Gain = 0.33 0.75
Gain = 0.25 1
Gerr Gain error Gain = 0.5 1.71V to 5.5V -0.3 2.7 %
Gain = 0.33 -0.7 5.0
Gain = 0.25 -0.7 4.7
Voltage Reference
VREF Internal VREF error TA = 25℃ VREF = 32mV to 512mV 1.71V to 5.5V -6.0 1 6.0 %
–40°C < TA ≤ 125°C -6.0 1 6.0
TA = 25℃ VREF = 544mV to 1024mV -6.0 0.95 6.0
–40°C < TA ≤ 125°C -6.0 0.95 6.0
TA = 25℃ VREF = 1056mV to 1504mV -6.0 0.9 6.0
–40°C < TA ≤ 125°C -6.0 0.9 6.0
TA = 25℃ VREF = 1536mV to 2016mV 2.3 V to 5.5 V -6.0 0.85 6.0
–40°C < TA ≤ 125°C -6.0 0.85 6.0
Analog Temperature Sensor
TERR Temperature sensor accuracy 10°C to 45°C 1.71V to 5.5V -1.8 4.3 ºC
-40°C to 85°C -4.9 5.2
-40°C to 105°C -6.1 5.2
-40°C to 125°C -9.4 5.2
TOUT Temperature sensor output -40°C 1.71V to 5.5V 1.232 1.254 V
-30°C 1.184 1.204
-20°C 1.138 1.158
-10°C 1.092 1.112
0°C 1.046 1.067
10°C 1.000 1.022
20°C 0.955 0.977
25°C 0.933 0.955
30°C 0.911 0.933
40°C 0.866 0.889
50°C 0.821 0.845
60°C 0.775 0.801
70°C 0.730 0.757
80°C 0.685 0.713
85°C 0.663 0.692
90°C 0.640 0.670
100°C 0.596 0.627
110°C 0.552 0.584
120°C 0.508 0.543
125°C 0.486 0.522
130°C 0.464 0.502
tDELAY Temperature sensor start-up delay 1.71V to 5.5V 70 100 µs
Analog Multiplexer
ron ON-state switch resistance –40°C < TA ≤ 125°C VI = 0V,
IO = 4mA		 1.8V ± 0.09V 35 Ω
VI = 1.71V,
IO = -4mA		 35
VI = 0V,
IO = 8mA		 2.5V ± 0.2V 32.5
VI = 2.3V,
IO = -8mA		 32.5
VI = 0V,
IO = 24mA		 3.3V ± 0.3V 30
VI = 3V,
IO = -24mA		 30
VI = 0V,
IO = 30mA		 5V ± 0.5V 25
VI = 2.4V,
IO = -30mA		 25
VI = 4.5V,
IO = -30mA		 25
rrange ON-state switch resistance over signal range 0 ≤ VA, VB ≤ VCC
–40°C < TA ≤ 125°C		 IO = -4mA 1.8V ± 0.09V 205 Ω
IO = -8mA 2.5V ± 0.2V 75
IO = -24mA 3.3V ± 0.3V 35
IO = -30mA 5V ± 0.5V 25
Δron Difference of ON-state resistance between switches  VA, VB = 1.15V
–40°C < TA ≤ 125°C		 IO = -4mA 1.8V ± 0.09V 0.5 Ω
 VA, VB = 1.6V
–40°C < TA ≤ 125°C		 IO = -8mA 2.5V ± 0.2V 0.3
 VA, VB = 2.1V
–40°C < TA ≤ 125°C		 IO = -24mA 3.3V ± 0.3V 0.3
 VA, VB = 3.15V
–40°C < TA ≤ 125°C		 IO = -30mA 5V ± 0.5V 0.2
ron(flat) ON-state resistance flatness 0 ≤ VA, VB ≤ VCC
–40°C < TA ≤ 125°C		 IO = -4mA 1.8V ± 0.09V 110 Ω
IO = -8mA 2.5V ± 0.2V 40
IO = -24mA 3.3V ± 0.3V 10
IO = -30mA 5V ± 0.5V 2
Ioff OFF-state switch leakage current 0 ≤ VI, VO ≤ VCC 1.71V to 5.5V ±7.5 µA
IS(on) ON-state switch leakage current VI = VCC or GND,
VO = Open		 5.5V ±0.1 ±2.5 µA
Cio(off) Switch input/output capacitance A, B 5V 9.5 pF
Cio(on) Switch input/output capacitance A, B 5V 20 pF
Y 20
(1) Open drain switching performance will be limited by pull-up resistors used